Tri-layer process for forming TFT matrix of LCD with reduced...

Details Tri-layer process for forming TFT matrix of LCD with reduced... Tri-layer process for forming TFT matrix of LCD with reduced...

2000-11-08

2001-08-14

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Including integrally formed optical element

C438S160000

Reexamination Certificate

active

06274400

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), and more particularly to a simplified tri-layer process for forming the TFT matrix with reduced masking steps.
BACKGROUND OF THE INVENTION
For conventional manufacturing processes of a TFTLCD, a tri-layer process and a back channel etch (BCE) process are main streams for forming the TFT matrix. Compared to a BCE structure, a tri-layer structure additionally includes an top nitride over the semiconductor layer as a etch stopper so that the etching step for defining a source/drain and channel region can be well controlled. Accordingly, the thickness of the active layer can be made to be thinner in the tri-layer structure than in the BCE structure, which is advantageous for the stability of resulting devices and performance in mass production. However, the provision of the additional etch stopper layer needs an additional masking step, thereby making the tri-layer process relatively complicated.
Conventionally, six to nine masking steps are required for either a BCE process or a tri-layer process. After the formation of the TFT matrix, a step of providing a black matrix around each pixel electrode region is generally required to improve the performance of the LCD. The provision of the black matrix after the process, however, will have difficulty in alignment.
On the other hand, the count of photo-masking and lithography steps directly affects not only the production cost but also the manufacturing time. Moreover, for each photo-masking and lithography step, the risks of mis-alignment and contamination may be involved so as to affect the production yield. Therefore, many efforts have been made to improve the conventional processes to reduce masking steps.
For example, for a BCE structure, U.S. Pat. Nos. 5,346,833 and 5,478,766 issued to Wu and Park et al., respectively, disclose 3 and/or 4 -mask processes for making a TFTLCD, which are incorporated herein for reference. By the way, it is to be noted that the 3-mask process for each of Wu and Park et al. does not include the step of forming and patterning of a passivation layer. If a passivation layer is required to assure of satisfactory reliability, the count of photo-masking and lithography steps should be four. Further, Wu and Park et al. use an ITO layer, which is integrally formed with the ITO pixel electrode, as the connection line between the TFT unit and the data line so that the area of the TFTLCD is limited due to the high resistivity of ITO.
As for the tri-layer structure, a conventional 6-mask process is illustrated as follows with reference to FIGS.
1
A~
1
G which are cross-sectional views of intermediate structures at different stages. The conventional process includes steps of:
i) applying a first conductive layer onto a glass substrate
10
, and using a first photo-masking and lithography procedure to pattern and etch the first conductive layer to form an active region
11
consisting of a scan line and a gate electrode of a TFT unit, as shown in
FIG. 1A
;
ii) sequentially forming tri-layers including an insulation layer
121
, a semiconductor layer
122
and an etch stopper layer
123
, and a photoresist
124
on the resulting structure of
FIG. 1A
, as shown in FIG.
1
B.
iii) using a second photo-masking and lithography procedure to pattern and etch the etch stopper layer
123
to form an etch stopper
13
which have a shape similar to the shape of the gate electrode, as shown in
FIG. 1C
;
iv) using a third photo-masking and lithography procedure to pattern and etch the semiconductor layer
122
to form a channel structure
14
, as shown in
FIG. 1D
;
v) sequentially applying a doped semiconductor layer and a second conductive layer on the resulting structure of
FIG. 1D
, and using a fourth photo-masking and lithography procedure to pattern and etch them to form source/drain regions
15
and data and connection lines
16
, as shown in
FIG. 1E
;
vi) applying a passivation layer
17
on the resulting structure of
FIG. 1E
, and using a fifth photo-masking and lithography procedure to pattern and etch the passivation layer
17
to create tape automated bonding (TAB) openings (not shown), and create a contact window
18
, as shown in
FIG. 1F
; and
vii) applying a transparent electrode layer on the resulting structure of
FIG. 1F
, and using a sixth photo-masking and lithography procedure to pattern and etch the transparent electrode layer to form a pixel electrode
19
, as shown in FIG.
1
G.
Six masking steps, however, are still too complicated.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a reduced mask process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the count of photo-masking and lithography steps can be reduced to three.
Another object of the present invention is to provide a tri-layer process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the connection line between a TFT unit and a data line has a relatively low resistivity compared to the ITO connection line so as to be suitable for a large-area TFTLCD.
According to a first aspect of the present invention, a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD) includes steps of providing a substrate made of an insulating material; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to remove a portion of the first conductive layer to define a scan line and a gate electrode of a TFT unit; successively forming an insulation layer, a semiconductor layer, an etch stopper layer, and a first photoresist layer on the substrate with the scan line and the gate electrode; providing a first exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as shields to obtain a first exposed area and a first unexposed area; removing the first photoresist layer, and the etch stopper layer of the first exposed area so that the remaining portion of the etch stopper layer in the first unexposed area has a specific shape similar to the shape of the scan line together with the gate electrode; forming a doped semiconductor layer and a second photoresist layer on the substrate with the etch stopper layer of the specific shape; providing a second exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as shields to obtain a second exposed area and a second unexposed area; removing the second photoresist layer, the doped semiconductor layer of the second exposed area, and the semiconductor layer of the second exposed area so that shapes of remaining portions of the doped semiconductor layer and the semiconductor layer in the second unexposed area are similar to that of the etch stopper layer of the specific shape, but have areas larger than that of the etch stopper layer of the specific shape, thereby making the doped semiconductor layer in contact with the semiconductor layer; successively forming a transparent conductive layer and a second conductive layer on the substrate, and using a second masking and patterning procedure to remove a portion of the transparent conductive layer and a portion of the second conductive layer to define a pixel electrode region and data and connection lines, respectively; removing another portion of the doped semiconductor layer with a remaining portion of the second conductive layer as shields to define source/drain regions; forming a passivation layer on the substrate, and using a third masking and patterning procedure to remove a portion of the passivation layer; and removing another portion of the second conductive layer with the patterned passivation layer as shields to expose the pixel electrode region.
When the exposing sources are light radiation, the insulating material is a light-transmitting material such as glass.
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