Nonvolatile writeable memory with preemption pin

Details Nonvolatile writeable memory with preemption pin Nonvolatile writeable memory with preemption pin

1996-09-20

2001-03-13

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

06201739

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of memory devices. More particularly, this invention relates to preempting an operation in a nonvolatile writeable memory.
BACKGROUND OF THE INVENTION
One type of prior art nonvolatile writeable memory is a flash Erasable and Electrically Programmable Read-Only Memory (“flash EPROM” or “flash memory”). A typical flash EPROM has the same array configuration as a standard Electrically Programmable Read-Only Memory (“EPROM”) and can be programmed in a similar fashion as an EPROM. Once programmed, either the entire contents of the flash EPROM or a block of the flash EPROM can be erased by electrical erasure in one relatively rapid operation. An erasing voltage is made available to the sources of all the cells in the flash EPROM or in one block of the flash EPROM. This results in a full array erasure or a block erasure. The flash EPROM or the erased block of the flash EPROM may then be reprogrammed with new data.
Flash EPROMs differ from convention Electrically Erasable Programmable Read-Only Memory (“EEPROMs”) with respect to erasure. Conventional EEPROMs typically use a select transistor for individual cell erasure control. Flash EPROMs, on the other hand, typically achieve much higher density with single transistor cells.
For a prior art single bit flash EPROM, a logical “one” means that few, if any, electrons are stored on a floating gate associated with a bit cell. A logical “zero” means that many electrons are stored on the floating gate associated with the bit cell. Erasure of the flash EPROM causes a logical one to be stored in each bit cell. Each single bit cell of the flash EPROM cannot be overwritten from a logical zero to a logical one without a prior erasure. Each single bit cell of that flash EPROM can, however, be written from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate associated with the erased state.
Flash EPROMs may be read, programmed (or written), and erased. For a prior art flash EPROM, a program operation to write a byte of data typically takes on the order of 10 microseconds. Because, however, there is some margin required for guaranteeing that the program operation has properly completed, a maximum program time is specified by the flash EPROM manufacturer. Thus, while the typical program operation may take 10 microseconds, the system may need to wait a maximum program operation time of 100 microseconds in order to guarantee that the program operation performed correctly.
Similarly, for a prior art flash EPROM, an erase operation may take from 300-600 milliseconds in order to erase a 8 kilobyte block of data. However, the flash EPROM may require up to a maximum erase operation time of 3 seconds in order to guarantee that the erase operation of the entire block of data has performed correctly.
Because the erase operation has such a long latency time, a prior art flash EPROM includes an erase suspend command. When an erase suspend command is written to the flash EPROM, the flash EPROM suspends the erase operation that is being performed. Other operations may then be performed on the flash EPROM. Subsequently, when an erase resume command is written to the flash EPROM) the flash EPROM resumes the erase operation from where its operation was suspended due to the erase suspend command. An implementation of the erase suspend circuitry is described in U.S. Pat. No. 5,355,464, entitled “Circuitry And Method For Suspending The Automated Erasure Of A Non-Volatile Semiconductor Memory,” by Fandrich et al., and issued to the common assignee of this application.
FIG. 1
shows a representation of a prior art flash EPROM
10
. The flash EPROM includes a command register
20
, memory array control circuitry
40
, and memory array
50
.
A number of data input/output (I/O) pins
12
are coupled from pins of the flash EPROM to a command register
20
. The number of data I/O pins
12
is usually 8 pins or 16 pins, which matches the size of data to be stored to the flash EPROM. The data I/O pins
12
allow commands to be written to the command register
20
. For example, for one prior art flash EPROM, the command decoder includes circuitry for decoding the following commands: (1) erase, (2) erase suspend, (3) erase resume, (4) program, (5) read, and (6) read status. A write enable (WE#) pin
30
is coupled to provide an input to the command register
20
.
The command register
20
is coupled to memory array control circuitry
40
via signal lines
78
a-n
. The memory array control circuitry
40
includes a status register
42
. The memory array control circuitry
40
also includes read circuitry, row and column decoder circuitry for accessing and providing data to cells in the memory array
50
, and a write state machine, which includes program and erase circuitry. The memory array control circuitry
40
provides the appropriate signals to access the memory array
50
for carrying out the commands provided by the command register
20
. The memory array control circuitry
40
receives an address input from address pins
44
of the flash EPROM. A command reset signal
48
is coupled from the memory array control circuitry
40
to the command register
20
.
The memory array is coupled to provide data to an output multiplexer
60
for providing data to the data I/O pins
12
of the flash EPROM responsive to a read operation. The status register
42
is also coupled to provide data to the output multiplexer
60
for providing status data to the data I/O pins
12
of the flash EPROM responsive to a read status operation. The status register
42
provides information about the current operation being executed by the flash EPROM. The memory array control circuitry
40
controls the output multiplexer
60
based upon the commands provided to it from the command register
20
. The memory array control circuitry
40
selects the status register output to pass through the output multiplexer
60
in response to a read status operation, and the memory array control circuitry selects the memory array output to pass through the output multiplexer
60
in response to a read operation.
In a prior art flash EPROM, a Ready/Busy (RY/BY#) pin
62
of the flash EPROM provides a status indicator of whether the flash EPROM is busy or not. The RY/BY# pin is “low” to indicate a busy state, which signifies that the flash EPROM is performing a block erase operation or a byte write operation. The RY/BY# pin is “high” to indicate a ready state, which signifies that the flash EPROM is ready for new commands, block erase is suspended, or the device is in a powerdown mode. The status register
42
is coupled to provide an output to the RY/BY# pin
62
.
Additionally, a supply voltage Vcc, ground potential Vss, and a programming voltage Vpp are provided to the flash EPROM
10
.
FIG. 2
shows a prior art block diagram of the command register
20
and the memory array control circuitry
40
. The command register
20
includes a command decoder
70
and command latches
76
a-n
. The command latches include an erase latch
76
a
, an erase suspend latch
76
b
, an erase resume latch
76
c
, a program latch
76
d
, a read latch
76
m
, and a read status latch
76
n.
The command decoder decodes the commands it receives from the data I/O pins
12
. Each of the commands are provided to an associated command latch
76
a-n
via the signal lines
72
a-n
. The command latches
76
a-n
latch the command upon assertion of the write enable (WE#) pin
30
. The command latches
76
a-n
provide the decoded command to the memory array control circuitry
40
via the signal lines
78
a-n.
The memory array control circuitry includes erase circuitry
90
, program circuitry
94
, read circuitry
96
, and read status circuitry
98
. Erase circuitry
90
includes erase suspend circuitry
92
. Read status circuitry
98
is coupled to the status register
42
.
The erase latch
76
a
, erase suspend latch
76
b
, and the erase resume latch
76
c
are coupled to erase circuitry
90
. The erase suspe

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