Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2000-01-12
2001-06-12
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06247110
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of computer architectures incorporating multiple processing elements. More particularly, the present invention relates to a multiprocessor computer architecture incorporating a number of memory algorithm processors in the memory subsystem to significantly enhance overall system processing speed.
All general purpose computers are based on circuits that have some form of processing element. These may take the form of microprocessor chips or could be a collection of smaller chips coupled together to form a processor. In any case, these processors are designed to execute programs that are defined by a set of program steps. The fact that these steps, or commands, can be rearranged to create different end results using the same computer hardware is key to the computer's flexibility. Unfortunately, this flexibility dictates that the hardware then be designed to handle a variety of possible functions, which results in generally slower operation than would be the case were it able to be designed to handle only one particular function. On the other hand, a single function computer is inherently not a particularly versatile computer.
Recently, several groups have begun to experiment with creating a processor out of circuits that are electrically reconfigurable. This would allow the processor to execute a small set of functions more quickly and then be electrically reconfigured to execute a different small set. While this accelerates some program execution speeds, there are many functions that cannot be implemented well in this type of system due to the circuit densities that can be achieved in reconfigurable integrated circuits, such as 64-bit floating point math. In addition, all of these systems are presently intended to contain processors that operate alone. In high performance systems, this is not the case. Hundreds or even tens of thousands of processors are often used to solve a single problem in a timely manner. This introduces numerous issues that such reconfigurable computers cannot handle, such as sharing of a single copy of the operating system. In addition, a large system constructed from this type of custom hardware would naturally be very expensive to produce.
SUMMARY OF THE INVENTION
In response to these shortcomings, SRC Computers, Inc., Colorado Springs, Colo., assignee of the present invention, has developed a Memory Algorithm Processor (“MAP”) multiprocessor computer architecture that utilizes very high performance microprocessors in conjunction with user reconfigurable hardware elements. These reconfigurable elements, referred to as MAPs, are globally accessible by all processors in the systems. In addition, the manufacturing cost and design time of a particular multiprocessor computer system is relatively low inasmuch as it can be built using industry standard, commodity integrated circuits and, in a preferred embodiment, each MAP may comprise a Field Programmable Gate Array (“FPGA”) operating as a reconfigurable functional unit.
Particularly disclosed herein is the utilization of one or more FPGAs to perform user defined algorithms in conjunction with, and tightly coupled to, a microprocessor. More particularly, in a multiprocessor computer system, the FPGAs are globally accessible by all of the system processors for the purpose of executing user definable algorithms.
In a particular implementation of the present invention disclosed herein, a circuit is provided either within, or in conjunction with, the FPGAs which signals, by means of a control bit, when the last operand has completed its flow through the MAP, thereby allowing a given process to be interrupted and thereafter restarted. In a still more specific implementation, one or more read only memory (“ROM”) integrated circuit chips may be coupled adjacent the FPGA to allow a user program to use a single command to select one of several possible algorithms pre-loaded in the ROM thereby decreasing system reconfiguration time.
Still further provided is a computer system memory structure which includes one or more FPGAs for the purpose of using normal memory access protocol to access it as well as being capable of direct memory access (“DMA”) operation. In a multiprocessor computer system, FPGAs configured with DMA capability enable one device to feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm located in the reconfigurable hardware. The system and method of the present invention also provide a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in programmable hardware.
Broadly, what is disclosed herein is a computer including at least one data processor for operating on user data in accordance with program instructions. The computer includes at least one memory array presenting a data and address bus and comprises a memory algorithm processor associated with the memory array and coupled to the data and address buses. The memory algorithm processor is configurable to perform at least one identified algorithm on an operand received from a write operation to the memory array.
Also disclosed herein is a multiprocessor computer including a first plurality of data processors for operating on user data in accordance with program instructions and a second plurality of memory arrays, each presenting a data and address bus. The computer comprises a memory algorithm processor associated with at least one of the second plurality of memory arrays and coupled to the data and address bus thereof. The memory algorithm processor is configurable to perform at least one identified algorithm on an operand received from a write operation to the associated one of the second plurality of memory arrays.
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Huppenthal Jon M.
Leskar Paul A.
Follansbee John A.
Hogan & Hartson LLP
Kubida William J.
SRC Computers, Inc.
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