Reproducing apparatus for reproducing data at a speed...

Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium

Reexamination Certificate

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Details

C386S349000

Reexamination Certificate

active

06219486

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an apparatus for reproducing a digital recording.
2. Related Background Art
There is known a recording method whereby information such as an image signal is digitally recorded onto a magnetic tape by a helical scan system. A recording method of interleave recording under predetermined rules is used in order to improve a picture quality for a burst or a signal dropout in a normal reproducing mode, a reproduction disable region in a special reproducing mode, or the like (for example, JP-A-63-306504).
FIG. 1
is a plan view of a rotary drum of such a helical scan type digital recording and reproducing apparatus.
FIG. 2
shows a development diagram of the rotary drum. Reference numeral
50
denotes a rotary drum;
52
A,
52
B,
54
A and
54
B, magnetic heads for recording or reproducing; and
56
, a magnetic tape. Each of the heads
52
A and
54
A has a plus azimuth angle. Each of the heads
52
B and
54
B has a minus azimuth angle. Each of the heads
52
A and
54
A is arranged so as to be away from each of the heads
52
B and
54
B by only a small angle &thgr; in the circumferential direction of the rotary drum
50
. Each of the heads
52
A and
52
B is arranged so as to be away from each of the heads
54
A and
54
B by an angle of 180° in the circumferential direction of the rotary drum
50
. In the recording or reproducing mode, a pair of heads
52
A and
52
B and another pair of heads
54
A and
54
B are alternately used.
FIG. 3
shows a recording format of a magnetic tape in case of using eight tracks per one frame. A+ denotes tracks which are recorded or reproduced by the magnetic heads
52
A and
54
A. B− indicates tracks which are recorded or reproduced by the magnetic heads
52
B and
54
B. Image data of an even field (field #0) are recorded to the former half four tracks. Image data of an odd field (field #1) are recorded to the remaining four tracks.
FIG. 4
shows a data structure of one picture plane. In case of the NTSC system, one frame has
512
horizontal scanning lines and the image data are divided into synchronizing blocks on a line unit basis. On the CRT screen shown in
FIG. 4
, a solid line indicates a line of the even field and a broken line denotes a line of the odd field. In a line data block L
n,m
, n de notes a distinction (0 or 1) of the field and m indicates a line number. Each of the synchronizing blocks comprises: a sync code (sync) to match the synchronization timing; an identification code (ID) to identify each synchronizing block; image data of the line; and an error detection correction code P.
FIG. 5
is a block diagram showing a construction of a recording system of a conventional apparatus.
FIG. 6
is a block diagram showing a construction of a reproducing system of the conventional apparatus.
In
FIG. 5
, an analog video signal to be recorded is supplied to an input terminal
10
. An A/D converter
12
converts the analog video signal from the input terminal
10
into a digital signal. A coding circuit
14
compresses and encodes the output data from the A/D converter
12
by, for example, a DPCM coding method. The compression coded image data from the coding circuit
14
are written into a frame memory
16
and is also supplied to an error detection correction coding circuit
18
. The coding circuit
18
generates the error detection correction code P to the compressed image data on a line unit basis and writes the resultant image data into the memory
16
. The memory
16
ordinarily has a memory capacity of two frames. An address generation circuit
20
generates a write address and a read address of the memory
16
.
A sync-ID addition circuit
22
adds a sync code (sync) and an ID for every line to the data read out from the memory
16
, thereby forming a line data block as shown in
FIG. 5. A
modulation circuit
24
modulates an output of the sync-ID addition circuit
22
(for example, converts the output into an NRZI signal). An output signal of the modulation circuit
24
is magnetically recorded onto a magnetic tape
28
by a magnetic head
26
. The magnetic head
26
corresponds to the magnetic heads
52
A,
52
B,
54
A and
54
B shown in
FIGS. 1 and 2
.
The reproducing system of
FIG. 6
will now be described. The magnetic recording signal on the magnetic tape
28
is electromagnetically converted by the magnetic head
26
. A demodulation circuit
30
demodulates the output of the magnetic head
26
and generates the digital signal of the line data block structure. A sync-ID separation circuit
32
separates the ID, image data, and error detection correction code P in accordance with the (sync) code sync from the line data block which is generated from the demodulation circuit
30
. The reproduction image data and the error detection correction code P are supplied to a memory
34
. The reproduction ID is supplied to an address generation circuit
36
.
The address generation circuit
36
generates write addresses of the memory
34
in accordance with the reproduction ID. The memory
34
also generally has a memory capacity of two frames. An error detection correction circuit
38
detects and corrects errors in the image data stored in the memory
34
with reference to the error detection correction code P of the memory
34
. The address generation circuit
36
generates a read address of the memory
34
, thereby, reading out from memory
34
the image data of the frame whose error detecting correcting processes have been finished in the memory
34
.
In case of reproducing the data at the same speed as that in the recording mode, the reproduction data are written into a first field memory area in the memory
34
in accordance with the ID of the line data block. In this instance, the data stored in another field memory area are read out. The memory area into which the data are written and the memory area from which the data are read out are changed for every field.
FIG. 7
shows a memory space of a memory having a memory capacity of one frame. The ordinate indicates an address and the abscissa shows a time. Data are written in accordance with arrows shown by solid lines. The recorded data are read out in accordance with arrows shown by broken lines. Since the reading and writing operations of data are executed for different field memory areas, an outrun of the memory access does not occur.
A decoding circuit
40
, shown in
FIG. 6
, executes a decoding process corresponding to the coding process in the coding circuit
14
to the data read out from the memory
34
and generates a digital image signal. A D/A converter
42
converts the digital output signal from the decoding circuit
40
into the analog signal. The analog signal is supplied from an output terminal
44
to a video monitor or the like.
In case of reproducing the data at the same speed as that in the recording mode, no problem occurs. In case of reproducing the data at a speed higher than that in the recording mode (hereinafter, such a reproduction is called a search reproduction), however, the magnetic head traces a plurality of tracks during each rotation.
FIG. 8
shows a trace pattern for search reproduction. That is, data of different fields coexist in one frame period. Therefore, the address generation circuit
36
generates a write address existing in both of the odd field memory area and the even field memory area in the memory
34
in accordance with the reproduction ID.
FIG. 9
shows the writing operation of the memory
34
. The ordinate indicates an address and the abscissa shows a time. Since the data are reproduced by irregular addresses, the data are also irregularly written into the memory
34
.
As mentioned above, since the writing operation is irregularly executed to the whole frame, there is no surplus time to read out the data. If the operator tries to forcedly read out data, the reading operation outruns the writing operation. To avoid such an outrun, hitherto, the frame memory having a memory capacity of at least two frames is used as a memory
34
an

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