Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-11-30
2001-01-09
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S695000, C438S706000, C438S720000
Reexamination Certificate
active
06171963
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing processes, and more particularly, to a method for forming a planar intermetal dielectric using a barrier layer.
BACKGROUND OF THE INVENTION
Intermetal dielectric layers are commonly used to isolate conductive structures, such as metal layers, from subsequently deposited conducting layers.
FIG. 1
shows a cross-sectional area of a semiconductor substrate
100
. Atop the substrate is a plug
102
in an interlayer dielectric
104
, a conductive structure
106
above the plug
102
, and an intermetal dielectric layer
108
. In a conventional method for forming the structure shown in
FIG. 1
, the metal layer forming the conductive structure
106
is overetched. Overetching of the metal layer is performed to ensure removal of metal residue. However, this overetching also causes a removal of a portion of the interlayer dielectric
104
, undesirably causing an increase in step height. The increased step height worsens the planarization of the subsequent intermetal dielectric
108
. In addition, the increased step height presents a keyhole problem. That is, voids
110
are created during the deposition of the intermetal dielectric layer
108
.
What is needed is a method for forming a planar intermetal dielectric layer that eliminates the aforementioned problems.
SUMMARY OF THE INVENTION
A method for forming a planar structure on a semiconductor substrate is disclosed. The method comprises the steps of: forming an interlayer dielectric atop said substrate; patterning and etching said interlayer dielectric, stopping at said substrate, to form a contact opening; forming a barrier metal layer on the bottom and sidewalls of said contact opening and atop said interlayer dielectric; depositing a conducting layer into said contact opening and atop said barrier metal layer; removing a portion of said conducting layer atop said barrier metal layer, leaving a plug in said contact opening; removing a portion of said barrier metal layer atop said interlayer dielectric; forming a cap barrier layer on exposed portions of said plug, said barrier metal layer, and said interlayer dielectric; and removing a portion of said cap barrier layer atop said plug.
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Blakely , Sokoloff, Taylor & Zafman LLP
Deo Duy-Vu
Utech Benjamin L.
Worldwide Semiconductor Manufacturing Corporation
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