Internal voltage boosting circuit

Details Internal voltage boosting circuit Internal voltage boosting circuit

1999-10-18

2001-09-04

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06285241

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an internal voltage boosting-up circuit, and more particularly to an internal voltage boosting-up circuit that generates an internally boosted voltage in a semiconductor storage device.
2. Background of the Invention
In the past, in order to achieve stable and efficient reading and writing of memory cell data in a semiconductor memory device, an internal voltage boosting circuit was provided to raise the potential on a word line connected to an n-channel MOS transistor of a memory cell to a voltage that is greater than the externally supplied power supply voltage.
FIG. 1
is a block diagram showing the configuration of a general internal voltage boosting-up circuit.
As shown in
FIG. 1
, a general voltage boosting circuit is formed by an oscillator circuit
1
to which is input an oscillator control signal
1
and which generates a signal having a prescribed frequency, and an boosted voltage generating circuit
4
which inputs the oscillation signal output of the oscillator circuit
2
and outputs a stepped-up voltage VBOOT.
FIG. 4
is a drawing that shows a specification configuration of a boosted voltage generating circuit shown in
FIG. 1
, provided for the purpose of describing an example of such a circuit in the related art.
As shown in
FIG. 4
, the boosted voltage generating circuit
4
has two voltage boosting circuits,
6
a
and
6
b.
The first voltage boosting circuit
6
a
has a delay element D
1
, to which an oscillator signal
3
is input, the output (node S
1
) of which is delayed by tD
1
, an inverter INVL for inverting the output of the delay element D
1
, an inverter INV
2
for inverting the output of the inverter INV
1
, a capacitance C
1
, one end of which is connected to the output (node S
3
) of the inverter INV
2
, and the other end of which is connected to a node S
4
, an NMOS transistor N
2
, the source and gate of which are connected to the power supply VDD, and the drain of which is connected to the node S
4
, an NMOS transistor N
3
, the source of which is connected to the power supply VDD, the drain of which is connected to the node S
4
, and the gate of which is connected to a node S
14
, an NMOS transistor N
4
, the source of which is connected to the node S
4
, the drain of which is connected to a node S
6
, and the gate of which is connected to the node S
14
, an NMOS transistor N
5
, the source of which is connected to the node S
4
, the drain of which is connected to the voltage boosted line VBOOT, and the gate of which is connected to a node S
6
, a NAND logic circuit NA
1
, the oscillator signal
3
and the output of the delay element D
1
being connected to the two inputs thereof, an inverter INV
3
for inverting the output of the NAND circuit NA
1
, and a capacitance C
2
, one end of which is connected to the output of the inverter INV
3
(node S
5
) and the other end of which is connected to the node S
6
.
The second voltage boosting circuit
6
b
has exactly the same configuration as the first voltage boosting circuit
6
a
, with the exception that, whereas the first voltage boosting circuit
6
a
inputs the oscillator signal
3
, the second voltage boosting circuit
6
b
inputs the inverted oscillator signal /
3
(bar
3
) from an inverter INV
4
.
Stated more explicitly, the second voltage boosting circuit
6
b
has a delay element D
2
, to which an oscillator signal /
3
, which is an inverted signal of the oscillation signal
3
, is input, the output (node S
11
) of which is delayed by tD
1
, an inverter INV
5
for inverting the output of the delay element D
2
, an inverter INV
6
for inverting the output of the inverter INV
5
, a capacitance C
3
, one end of which is connected to the output (node S
13
) of the inverter INV
6
, and the other end of which is connected to a node S
14
, an NMOS transistor N
7
, the source and gate of which are connected to the power supply VDD, and the drain of which is connected to the node S
14
, an NMOS transistor N
8
, the source of which is connected to the power supply VDD, the drain of which is connected to the node S
14
, and the gate of which is connected to the node S
4
, an NMOS transistor N
9
, the source of which is connected to the node S
14
, the drain of which is connected to a node S
16
, and the gate of which is connected to the node S
4
, an NMOS transistor N
10
, the source of which is connected to the node S
14
, the drain of which is connected to the voltage boosted line VBOOT, and the gate of which is connected to the node S
16
, a NAND logic circuit NA
2
, the inverted oscillator signal /
3
and the output S
11
of the delay element D
2
being connected to the two inputs thereof, an inverter INV
7
for inverting the output of the NAND circuit NA
2
, and a capacitance C
4
, one end of which is connected to the output of the inverter INV
7
(node S
15
) and the other end of which is connected to the node S
16
.
The operation of the voltage boosting circuit
4
shown in
FIG. 4
is described below, with reference being made to signal waveform diagrams.
FIG. 5
is a set of potential waveform diagrams for various nodes in the first voltage boosting circuit
6
a
of a boosted voltage generating circuit
4
according to the related art, as shown in FIG.
4
.
As shown in
FIG. 5
, when the oscillator signal
3
is at the low level (L), because the node S
14
, which is the gate voltage of the NMOS transistors N
3
and N
4
is at a voltage of (VDD+&Dgr;VBOOT), the NMOS transistors N
3
and N
4
are in the on condition at this time, so that the nodes S
4
and S
6
are at the voltage VDD.
When the oscillator signal
3
changes from the low level to the high level (H), the capacitances C
1
and C
2
are charged with a delay of tD
1
, in accordance with the delay element D
1
, so that the voltage at the nodes S
3
and S
5
change from ground (GND) to VDD. When this occurs, the nodes S
4
and S
6
, which are the other ends of the capacitances C
1
and C
2
, which are in the floating condition, change by the amount &Dgr; VBOOT, according to the law of stored charges. That is, in the case in which the capacitances C
1
and C
2
are sufficiently larger than parasitic capacitances at the nodes S
4
and S
6
, &Dgr; VBOOT is approximately equal to the changing voltage VDD.
As a result of the increase in potential at the node S
6
, the NMOS transistor N
5
changes to the on condition, so that a charge is transferred from the node S
4
to the stepped-up voltage line VBOOT, the stepped-up voltage line VBOOT being thereby biased by the boosted-up voltage VBOOT.
Thus, in an internal voltage boosting circuit
4
of the past, by repeating the voltage waveforms on the nodes S
4
and S
6
are repeated, so as to generate the internally stepped-up voltage VBOOT.
Because the potentials on the various nodes of the second voltage boosting circuit
6
b
is the same as those on the nodes of the first voltage boosting circuit
6
a
, with the only difference being that the phases are reversed, these will not be explicitly described herein.
With recent increased demand for more compact portable electronic equipment, limitations have been placed on power supplies, and it is additionally required that operation over longer periods of time than in the past be achieved within these power supply limitations.
With this operating environment as a backdrop, there is an even further need for a reduction in the power consumption of semiconductor memory devices.
Accordingly, the present invention was made in consideration of the above-noted drawbacks in the related art, and has as an object the provision of an internal voltage boosting circuit that provides the capacity available in the past, while achieving a reduction in power consumption.
SUMMARY OF THE INVENTION
To achieve the above-noted object, the present invention has the following basic technical constitution.
In a first aspect of the present invention, an internal voltage boosting circuit is provided in which the internal voltage boosting circuit comprises a plurality of voltage

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