Information processing system having a plurality of processors

Details Information processing system having a plurality of processors Information processing system having a plurality of processors

1993-08-30

1996-01-02

Harvey, Jack B.

395736, 395729, G06F 1314

Patent

active

054817269

ABSTRACT:
An information processing system including processors, and an interrupt controller responsive to an interrupt request signal from the processors for executing an interrupt process control of processes carried out by the processors. The interrupt controller includes an interrupt process execution device that does not have a multiple interrupt processing function, and an interrupt acceptance device. The interrupt acceptance device has an interrupt reservation signal input terminal, and responds to an interrupt request signal for making determination whether an interrupt is permitted. If interrupt is permitted, an interrupt request generation signal is applied to a corresponding interrupt request generation signal input terminal of the interrupt process execution device. Each of the processors includes an interrupt request signal output circuit and a processing circuit. The interrupt reservation signal output circuit generates and provides to an interrupt reservation signal input terminal of the interrupt acceptance device an interrupt reservation signal prior to an output of an interrupt request signal from the interrupt request signal output circuit. By applying an interrupt reservation signal to the interrupt reservation signal input terminal from the particular processor, an interrupt request signal generated from another processor can not be accepted during the time thereof.

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