Boots – shoes – and leggings
Patent
1993-10-14
1996-02-13
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, H03K 1900
Patent
active
054916399
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
A main reason for unexpected delays and additional costs are errors in the design phase of digital circuits. To avoid these, various simulation procedures are currently used for verifying a logical circuit design. Unfortunately, the number of simulations needed for verifying a circuit or a data-processing system grows exponentially with the number of inputs of combinatorial circuits and even faster for sequential circuits since all possible input sequences must be simulated in these. Although such methods for simulating digital circuits are widely used and have an important place in the design process of such circuits, they are far from suitable for completely checking and verifying circuits which is why the correctness of a circuit, that is to say the correspondence between its actual implementation and its design specification cannot be guaranteed. For this reason, formal verification methods must be preferred to any type of simulation since, in principle, these can prove the complete correctness of a circuit.
Specifications of combinatorial or synchronous sequential circuits are frequently formulated in the form of so-called hardware description languages (HDL). In these cases, formal verification means the comparison of a digital circuit such as is given, for example, in the form of a network list, with its specification in the form of a description, using the methods of a hardware description language. From the literature (Erik Tiden, Richard Schmid, "Verifying ASICs in symbolic simulation", in EURO ASIC 90, 1990), formal circuit verification tools are known, the applicability of which, however, is restricted to combinatorial circuits. The formal verification of sequential digital circuits is much more difficult and only a few approaches to a solution to the problem of verifying digital circuits with a large number of states are known.
SUMMARY OF THE INVENTION
The invention relates to a procedure for verifying data-processing systems, particularly digital circuits, which is based on the symbolic representation of boolean functions with the aid of binary decision diagrams. The invention is based on the object of specifying a procedure for verifying data-processing systems, particularly digital circuits, which is capable of verifying not only combinatorial but also sequential systems of high complexity and thus to overcome the problems of the procedures known in the prior art. This object is achieved with the aid of a procedure for verifying data-processing systems, particularly digital circuits, having the following steps.
Like the procedure known from the prior art, this procedure is also based on the comparison between two formal descriptions, generated independently of one another, of a system to be verified, for example the system specification formulated with the aid of a hardware description language and the circuit implementation present, for example, in the form of a network list. The procedure according to the invention uses a special representation of boolean functions with the aid of binary decision diagrams or equivalent means. This special and advantageous representation of boolean functions enables the comparison of both system descriptions to be carried out with the aid of a fixed-point iteration, with the aid of which non-equivalent states of the two system descriptions are found. For this purpose, the two system descriptions to be compared with one another are modeled as Mealy automata. The fixed-point iteration is used for representing the set of non-equivalent states of the two Mealy automata in the form of binary decision diagrams or equivalent means. To carry out the fixed-point iteration, the output and transitional functions of the two Mealy automata are also represented by binary decision diagrams or equivalent means.
The form of representation by binary decision diagrams according to the invention produces an extremely efficient storage of the data structures of the procedure and enables the operations necessary for carrying out the procedure to
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Frejd Russell W.
Siemens Aktiengesellschaft
Teska Kevin J.
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