Selective slurries for the formation of conductive structures

Details Selective slurries for the formation of conductive structures Selective slurries for the formation of conductive structures

1999-12-16

2001-06-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S584000, C438S622000, C438S628000, C438S631000, C438S633000, C438S637000, C438S639000, C438S648000, C438S687000, C438S692000, C438S696000

Reexamination Certificate

active

06251789

ABSTRACT:

FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a novel chemical-mechanical slurry and a method of selectively removing a conductive structure while leaving the underlying liner layer substantially non-removed.
BACKGROUND OF THE INVENTION
Two trends present in the semiconductor device-manufacturing arena involve the desire to have planar structures and lessening the resistivity of conductive structures. Chemical-mechanical polishing (CMP) is being utilized with greater and greater frequency to achieve both of these trends. Most semiconductor manufacturers use CMP to planarize interlevel dielectric layers and to planarize some metal structures. The most common approach used in the CMP industry is to attach a semiconductor wafer to a carrier (which may or may not rotate) via a mounting pad and polish the exposed surface of the wafer by bringing it into contact with a polishing pad (which is mounted on a rotating or non-rotating platen). The mechanical abrasion between the wafer surface and the polishing pad results in the polishing of the wafer surface. To aid in the polishing and the removal of any particles liberated in this process, slurry can be introduced between the wafer surface and the polishing pad. The slurry will interact with the wafer surface thereby making the wafer more easily polishable and the excess slurry will carry away the materials liberated from the wafer during this polishing step.
Most processes used in the semiconductor industry, today, involve the formation of a layer of either conductive or insulating material followed by the planarization (typically CMP) of the material. For example, a dielectric layer, which is quite thick in comparison to other structures, is typically deposited over the entire wafer. Due to the underlying topology the upper surface of this layer varies in height by a fairly appreciable amount. Using present lithography methods and equipment, the via holes/trenches, that are to be patterned in this layer to form the conductive interconnects, are difficult to fabricate because of the variance in the height of this upper surface. Hence, a planarization step is required prior to the patterning of these holes. This step is, typically, accomplished by CMP, which results in a relatively planar upper surface of the dielectric layer.
In addition, CMP is being utilized after the blanket formation of a conductive material (such as tungsten, copper, aluminum, or other metal) so as to form inlaid conductive structures such as vias and/or interconnects. In fact, some conductive structures, e.g. copper structures, are not easily formed without using CMP because there really does not exist an etchant which effectively removes copper without substantially degrading the layers which underlie the copper structure. The use of CMP, as opposed to, for example, reactive ion etching (“RIE”), is both cleaner and results in a more planar structure. Typically, metallization schemes are formed using CMP by first forming the openings in a dielectric layer for the vias and/or interconnects and then forming a blanket (or selectively) coating of the conductive material so as to fill up the vias and/or interconnect openings. In order to properly fill these openings, an excess amount of the conductor is preferably formed over the wafer. This results in the formation of the conductive material over the dielectric layer in regions other than the openings. In order to remove this excess material, a CMP process is performed.
In order to reduce the resistivity of the conductors which span the largest part of the device and which carry a majority of the signals, most device manufacturers are trying to utilize copper for their upper level conductors. While copper has better electromigration properties and lower resistivity than traditional conductors, e.g. aluminum and tungsten, copper is more difficult to pattern because, at present, there does not exist an effective copper etchant which does not substantially degrade the structures which underlie the copper structure. Hence, many device manufacturers are trying to use CMP to form the copper structures. As was stated above, the CMP process is used to not only remove the excess portion of copper which overlies the dielectric layer but also to remove the barrier/liner layer which underlies the copper layer. This underlying layer is important because it helps promote the adhesion of the copper layer to the wafer and it provides a barrier between the copper structure and the dielectric layer. The conventional practice and all of the research efforts geared at coming up with new slurries and CMP techniques involve the removal of both the excess copper and liner/barrier layers in one step using one CMP tool and a single slurry. However, the removal of both of these layers can cause “dishing” of the copper structure and erosion of the underlying dielectric layer.
SUMMARY OF THE INVENTION
An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer on the upper surface of the patterned dielectric layer and on the bottom and the sidewalls of the opening in the patterned dielectric layer; forming a conductive layer on the liner layer; removing the portion of the conductive layer which overlies the top surface of the dielectric layer thereby exposing a portion of the liner layer while leaving the portion of the conductive layer situated in the opening of the dielectric layer substantially unremoved, the step of removing the portion of the conductive layer is accomplished by chemical mechanical polishing using a first slurry; removing the exposed portion of the liner layer while leaving the unexposed portion of the liner layer substantially unremoved by chemical mechanical polishing using a second slurry; and wherein the first slurry removes the conductive layer much more readily than the liner layer and the second slurry removes the liner layer more readily than the conductive layer. Preferably, the liner layer is comprised of: Ta, TaN, Ta/TaN stack, Ti, TiN, a Ti/TiN stack, a refractory metal, and any combination thereof, and the conductive layer is comprised of: copper, a copper alloy, tungsten, aluminum, a refractory metal, and any combination thereof. The first slurry, preferably, removes around 100 parts (or around 50 parts, or around 20 to 30 parts or around 15 parts) of the conductive layer to every one part of the liner layer. Preferably, the second slurry has a pH around 11 to 12, and is comprised of particulate and a wetting agent. The particulate is, preferably, around 2 to 5 percent by weight of the total composition of the second slurry. Preferably, the second slurry removes around 20 parts (or preferably around 12 parts or preferably around 10 parts) of the liner layer to every one part of the conductive layer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1
a
-
1
d
are cross-sectional views of a partially fabricated device, which is fabricated using the method of one embodiment of the instant invention.
FIG. 2
is a graph of measured data where the vertical axis represents the measured reflectance off of a wafer as it is chemical-mechanically polished using the method of the instant invention.


REFERENCES:
patent: 5960317 (1999-09-01), Jeong
patent: 6071816 (2000-06-01), Watts et al.
patent: 6083840 (2000-07-01), Mravic et al.

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