Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1994-09-01
2001-05-01
Talbot, Brian K. (Department: 1762)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C427S079000, C427S080000, C029S025030, C029S025410, C438S239000, C438S253000, C438S396000, C438S692000, C438S693000
Reexamination Certificate
active
06225133
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thin film capacitor adapted for integrated circuits and a method of manufacturing the same.
Conventionally, in a thin film capacitor adapted for semiconductor integrated circuit, a lamination structure using a polysilicon film for the upper and lower electrodes and a silicon oxide film and a silicon nitride film for the dielectric film has been used. In the dynamic random access memory (DRAM), a technique in which a capacitor portion is formed after the transistor and the bit line are formed is described (see, for example, “International Electron Devices Meeting Digest of Technical Papers”, 1988, page 592 through 595).
In the foregoing conventional thin film capacitor, it has been recognized that there is a limit posed to the reduction of the area of the capacitor portion so as to correspond to the recent high degree of the integrated circuit. Therefore, it is necessary to effectively reduce the area of the capacitor portion by thinning the dielectric film of the thin film capacitor, making it highly dielectric and stereoscopic. Since the dielectric film forming the conventional capacitor comprises a film of silicon oxide or silicon nitride having the dielectric constant on the order of at most 7, in order to achieve the required capacitive value, and an extremely thin film thickness of below 5 nm which is called for in terms of that of the silicon oxide film.
On the other hand, for such a thin film thickness, it is very difficult to realize a dielectric thin film having a current/voltage characteristic which is below the allowable leak current, and even if a method of increasing the area of the electrode effectively by using the three-dimensional structure is used, then the dielectric film becomes thin at the lower electrode, where the electric field is concentrated causing increase of the leak current.
Therefore, it is conceivable to realize the required capacitor with a greater film thickness than that of the silicon oxide film or the like by using a highly dielectric thin film typically represented by SrTiO
3
having a dielectric constant close to, for example, 300 at the room temperature, or (Ba, Sr)TiO
3
, Pb(Zr, Ti)O
3
, Pb(Mg, Nb)O
3
and Pb(Mg, W)O
3
having a further greater dielectric constant for barrier metal to suppress the diffusion of silicon and by using Pt/Ta, Pt/Ti and RuO
2
, which form no low dielectric layer even within the oxidizing atmosphere in which the highly dielectric film is deposited.
However, even in this case, if large corrugated portions are present on the primer base on which the highly dielectric thin film is deposited, since the leak current is increased, an excellent capacitor cannot be realized. In particular, if the capacitor is formed after a contact hole is provided through the interlayer insulating film and the like, the flattenability of the surface of the polysilicon layer after the contain hole is embedded becomes a problem.
Usually, the polysilicon layer is deposited according to the CVD process in such a thickness that the contact hole can fully be embedded, is reduced in resistance by diffusing an impurity into this layer, and then is etched back according to the dry etching process using Cl
2
to remove its unnecessary portions. However, in the etch-backing according to such dry etching, if the surface of the interlayer insulating film merges due to the microloading effect, then the etching speed rises rapidly, and up to the polysilicon layer within the contact hole is overetched. The overetched amount at this time, if a 6-inch wafer is used, amounts to 200 through 300 nm within the wafer surface, and the surface of the polysilicon layer also forms several ten nms of convex and concave portions.
When the barrier metal layer, highly dielectric thin film and the electrically conductive film adapted for the upper electrode are deposited on the primer base having such steps, it is difficult to obtain the leak current characteristic with excellent repeatability as they are deposited on a flat substrate due to the presence of the steps around the contact hole and of the convex and concave portions of the surface of the polysilicon layer.
Furthermore, in the thin film capacitor array using the highly dielectric film, even when the etch back of a second interlayer insulating film is applied to separate between each capacitor, according to the dry etching by CF
4
gas or the like, it is difficult to remove the interlayer insulating film evenly within the wafer surface.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a method of manufacturing a thin film capacitor comprising the steps of:
depositing an interlayer insulating film on a semiconductor substrate;
forming one or more contact holes at a desired position of said interlayer insulating film;
depositing a polysilicon layer to embed said contact hole(s);
flattening the surface of said polysilicon layer by chemical and mechanical polishing using at least one of piperazine and colloidal silica slurry; and
depositing on the flattened polysilicon layer a barrier metal film, a highly dielectric thin film and an electrically conductive film for the upper electrode and then processing those films to have a predetermined size.
In order to solve the problems of overetching and of the occurrence of the convex and concave portions of the surface as occur when the foregoing polysilicon layer is etched back, in the method according to the present invention, the flattenability of the surface is achieved by using not the dry etching process, but a chemical and mechanical polishing process using piperazine or colloidal silica slurry, to etch back the polysilicon layer to suppress the increase of the leak current.
Furthermore, in order to solve the problem of overetching as occurs when the second interlayer insulating film is etched back, in the present invention, the surface is flattened by using the chemical and mechanical polishing process utilizing the colloidal silica slurry to thereby suppress the increase of leak current to improve the evenness within the surface and the repeatability.
REFERENCES:
patent: 5185689 (1993-02-01), Maniar
patent: 5332684 (1994-07-01), Yamamichi et al.
patent: 5366920 (1994-11-01), Yamamichi et al.
patent: 5406447 (1995-04-01), Miyazaki
T. Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs”, International Electron Devices Meeting Digest of Technical Papers, 1988, pp. 592-595.
K. Koyama et al., “A Stacked Capacitor with (BaxSr1-xTIO3For 256M DRAM”, International Electron Devices Meeting Digest of Technical Papers, 1991, pp. 823-826.
Miyasaka Yoichi
Watanabe Hirohito
Yamamichi Shintaro
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Talbot Brian K.
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