Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-01-06
2001-05-15
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S175000, C327S291000, C327S299000
Reexamination Certificate
active
06232807
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pulse generating circuit, and more specifically to a pulse generating circuit capable of generating an internal clock pulse having a constant pulse width independent of the duty of an external input clock signal.
In a semiconductor device operating in synchronism with an input clock signal supplied from an external control system, it is assumed that a time required for an internal operation in the semiconductor device is for example 1.5 ns and a time required for a resetting operation is for example 1.5 ns, and further, an active operation is executed at a high level “H” of a clock signal and the resetting operation is executed at a low level “L” of the clock signal and a cycle of the clock signal is 4 ns. In this case, if the width of the high level “H” of an internal clock is set at about 2 ns, both the active operation and the resetting operation can be executed with a margin of about 0.5 ns.
However, if the width of the high level “H” of the internal clock varies dependently upon the duty of an external clock signal, the active operation cannot be executed with the high level width of 1 ns, nor can the resetting operation be executed with 1 ns.
In order to avoid the above mentioned inconvenience, a pulse generating circuit capable of generating an internal clock signal independently upon the duty of the external clock signal, has been proposed as shown in FIG.
6
.
The pulse generating circuit shown in
FIG. 6
includes an oscillator circuit
21
responding to a low-to-high transition of an input clock signal to generate a downward pulse, a P-channel MOS transistor
22
having a source connected to a high voltage supply, a gate connected to an output of the oscillator circuit
21
, and a drain connected to an output line
28
, an N-channel MOS transistor
23
having a drain connected to the output line
28
, a gate connected to an output of another oscillator circuit
25
and a source connected to ground, a delay circuit
24
having an input connected to the output line
28
and an output connected to an input of the oscillator circuit
25
, the oscillator circuit
25
having the input connected to the output of the delay circuit
24
and the output connected to the gate of the N-channel MOS transistor
23
, and another N-channel MOS transistor
26
having a drain connected to the output line
28
, a gate connected to a power-on circuit
27
and a source connected to the ground.
Now, an operation of the prior art pulse generating circuit shown in
FIG. 6
will be described. When the output of the prior art pulse generating circuit shown in
FIG. 6
is at a low level “L” in an initial condition, the oscillator circuit
21
generates the downward pulse in response to the low-to-high transition of the input clock signal. If the oscillator circuit
21
generates the downward pulse, the P-channel MOS transistor
22
is turned on so that the output line
28
of the pulse generating circuit is brought to a high level “H”.
In response to the low-to-high transition of the output line
28
, the oscillator circuit
25
generates an upward pulse after a delay of the delay circuit
24
, and the upward pulse is applied to the gate of the N-channel MOS transistor
23
. As a result, the N-channel MOS transistor
23
is turned on so that the output line
28
of the pulse generating circuit is brought to a low level “L”.
Thus, in the pulse generating circuit shown in
FIG. 6
, even if the pulse width of the external input clock signal is shorter than a required pulse width of the internal pulse, the internally generated pulse can have a constant pulse width, which is determined by the delay amount of the delay circuit
24
.
In the pulse generating circuit shown in
FIG. 6
, however, if the output of the pulse generating circuit is the high level “H” in the initial condition, the output of the delay circuit
24
which should delay the low-to-high transition of the output of the pulse generating circuit, remains fixed at the high level “H” as shown in FIG.
7
. Therefore, the output of the oscillator circuit
25
which should generate the upward pulse in response to the low-to-high transition in the output of the delay circuit
24
, also remains fixed at the low level “L”. As a result, the output of the pulse generating circuit remains fixed at the high level “H”, regardless of the input clock signal.
In order to the prevent the just above mentioned inconvenience, the pulse generating circuit shown in
FIG. 6
includes the power-on circuit
27
, which operates to forcibly bring the output to the low level “L” at a power-on time. As shown in
FIG. 8
, when a power supply voltage Vcc is rising as the result of the power-on, if the power supply voltage Vcc exceeds a predetermined level, the power-on circuit
27
turns on the N-channel MOS transistor
26
to forcibly brings the output to the low level “L”. However, since the power-on circuit does not operate in a situation other than the power-on time, the above mentioned inconvenience cannot be completely overcome.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a pulse generating circuit which has overcome the above mentioned problem of the prior art.
Another object of the present invention is to provide a pulse generating circuit capable of realizing a normal pulse generating operation even if the output level is at the high level in the initial condition.
The above and other objects of the present invention are achieved in accordance with the present invention by a pulse generating circuit comprising a first pulse generating means receiving an input clock signal for generating a first pulse in synchronism with the clock signal, a first P-channel MOS transistor having a source connected to a high voltage supply, a gate connected to an output of the first pulse generating means and a drain connected to an output line, a first delay means having a first predetermined delay time and having an input connected to the output line, a second pulse generating means having an input connected to an output of the first delay means, for generating a second pulse in synchronism with a level transition of the output of the first delay means, a first N-channel MOS transistor having a drain connected to the output line, a gate connected to an output of the second pulse generating means and a source connected to ground, and a detecting means connected to the output of the first pulse generating means and also connected to the output line, for bringing the output line to a low level when the input clock signal changes from a low level to a high level in the condition that the output line is at a high level.
In one embodiment of the above mentioned clock generating circuit, the detecting means includes a second delay means having a second predetermined delay time and having an input connected to the output line, an inverter means having an input connected to the output of the first pulse generating means, an AND circuit receiving an output of the inverter means and an output of the second delay means, and a second N-channel MOS transistor having a drain connected to the output line, a gate connected to an output of the AND circuit and a source connected to the ground.
Preferably, the second predetermined delay time of the second delay means is longer than a pulse width of the first pulse generated by the first pulse generating means. In addition, the first pulse generating means generates a downward pulse, and the second pulse generating means generates an upward pulse.
According to another aspect of the present invention, there is provided a pulse generating circuit comprising a first pulse generating means receiving an input clock signal for generating a first pulse in synchronism with the clock signal, a first N-channel MOS transistor having a drain connected to an output line, a gate connected to an output of the first pulse generating means and a source connected to ground, a first delay means having a first predetermined delay time and having an i
Cunningham Terry D.
Hayes, Soloway, Hennesse Grossman & Hage, P.C.
NEC Corporation
Tra Quan
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