Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-12-23
2001-08-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06274395
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor wafer fabrication, and more particularly to a method and apparatus for maintaining test data during fabrication of a semiconductor wafer.
BACKGROUND OF THE INVENTION
The manufacture of semiconductor wafers to create semiconductor integrated circuit devices typically involves the fabrication of a plurality of die on a single wafer. Each of the die are fabricated from a sequence of processing steps which create the multi-layer structure generally associated with integrated circuit devices. Such processing steps may include (1) the deposition of metals, dielectrics, and semiconductor films, (2) the creation of masks by lithography techniques, (3) the doping of semiconductor layers by diffusion or implantation, (4) the polishing of outer layers (e.g. chemical-mechanical polishing), and (5) the etching of layers for selective or blanket material removal.
During manufacture of integrated circuit devices, each individual die is tested prior to separation from the wafer. Such testing may include visual and electrical tests designed to distinguish “good” die from unusable or “bad” die. Such testing may also be designed to determine certain parametric characteristics about each die such as the voltage range, temperature range, or speed range at which the die operates.
Once tested, each individual die must be marked or somehow identified so that the die can be properly handled during the die separation and packaging processes. In particular, if a die fails one or more tests, it must be marked or otherwise identified such that the die may be disregarded. Conversely, if a die passes all tests, it must be marked or otherwise identified in order for the die to be presented to subsequent processing steps (e.g. packaging). It should be appreciated that a high degree of accuracy in the marking or identifying scheme is desirable. For example, if a die which failed one or more test is inadvertently packaged, the defective device may ultimately be sold thereby causing the system into which it is incorporated to potentially fail.
Accordingly, a number of wafer marking methods have heretofore been designed. One common marking method is wafer scribing. Wafer scribing utilizes a laser or the like to mechanically scribe information into a surface of the wafer. However, mechanical scribing is slow, costly, and the amount of information which may be written at a single location is relatively limited. Moreover, laser scribing is a “write once” method of recording information. In particular, once information has been scribed into a certain portion of the wafer, the same portion generally can not be utilized again to scribe additional information into the wafer. Because of these limitations, wafer scribing has generally only been utilized to record static information such as a wafer identification code, lot/date code, or part number.
Another wafer marking method is inking. Wafer inking is a process by which an ink mark such as a dot is placed on each die to indicate the pass/fail status of each die. However, similarly to wafer scribing, wafer inking is a write once method since the ink utilized in such a method is designed to be relatively difficult to remove from the die so as to prevent inadvertent removal thereof. Moreover, the number of categories into which a die may be divided is limited by the number of different ink colors which can be identified by a color detection device such as a calorimeter. In particular, if the particular type of testing performed sorts the die into different groups based on, for example, operative speed of the die, a different color of ink must be utilized for each group. If the number of desirable groups exceeds the number of different ink colors available, alternate marking schemes must be utilized thereby reducing the efficiency of the fabrication process.
A more recent approach to wafer tracking is the use of electronic files stored on a floppy disk or a network storage device. In such a method, a file containing test data such as pass/fail data associated with each of the die fabricated on a given wafer is stored on the floppy disk or network storage device. During packaging, the information is retrieved from the floppy disk or network storage device so as to determine which die passed testing and which die failed. However, it should be appreciated that this approach is susceptible to mistakes if the correlation between a particular wafer and its electronic file becomes mixed with that of another wafer.
Thus, a continuing need exists for a wafer marking and/or identifying method which overcomes one or more of the above mentioned drawbacks.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a method of fabricating a semiconductor wafer. The method includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. Moreover, the method includes the step of storing the test data obtained during the testing step in the memory device.
Pursuant to another embodiment of the present invention, there is provided a method of fabricating a semiconductor wafer. The method includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data.
Pursuant to yet another embodiment of the present invention, there is provided a semiconductor wafer. The semiconductor wafer includes a number of die fabricated on a first side of the wafer. The semiconductor wafer also includes a memory device fabricated on the first side of the wafer. The memory device has stored therein test data associated with each of the number of die.
Pursuant to another embodiment of the present invention, there is provided a semiconductor wafer. The semiconductor wafer includes a number of die fabricated on a first side of the wafer. The semiconductor wafer also includes a memory device fabricated on the first side of the wafer. The memory device is configured to store test data associated with each of the number of die.
It is therefore an object of the present invention to provide a new and useful semiconductor wafer.
It is also an object of the present invention to provide an improved semiconductor wafer.
It is further an object of the present invention to provide a new and useful method of fabricating a semiconductor wafer.
It is moreover an object of the present invention to provide an improved method of fabricating a semiconductor wafer.
It is a further object of the present invention to provide a method of maintaining test data associated with a semiconductor wafer during fabrication thereof which does not require inking or scribing of the wafer.
It is also an object of the present invention to provide a method of maintaining test data associated with a semiconductor wafer during fabrication thereof which does not reduce the size of the active area of the wafer.
The above and other objects, features, and advantages of the present invention will become apparent from the following description and the attached drawings.
REFERENCES:
patent: Re. 33947 (1992-06-01), Shinohara
patent: 3814895 (1974-06-01), Fredriksen
patent: 4543464 (1985-09-01), Takeuchi
patent: 4747093 (1988-05-01), Benne et al.
patent: 4933205 (1990-06-01), Duley et al.
patent: 5206181 (1993-04-01), Gr
LSI Logic Corporation
Niebling John F.
Stevenson André C.
LandOfFree
Method and apparatus for maintaining test data during... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for maintaining test data during..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for maintaining test data during... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2439733