Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
1996-07-15
2001-08-28
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S206000, C257S207000
Reexamination Certificate
active
06281529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device, and, more particularly, to a technique for accomplishing a multipin structure which provides a greater number of external pins.
2. Description of the Related Art
As semiconductor fabrication process has advanced, the integration architecture of semiconductor devices has become greater and the number of circuits formed on a single semiconductor chip tends to increase. Accordingly, there is a demand for a greater number of external pins (multipin structure). The multipin structure requires that the input/output pad pitch arranged along the periphery of a semiconductor chip should be shortened. In addition, it is necessary to shorten the widths of the input/output cell areas, which are arranged along the periphery of a semiconductor chip and lie to the interior of the pads. Once the input/output cell areas are formed, input/output circuits are constructed within the cells.
A gate array is one type of semiconductor integrated circuit (IC) device.
FIG. 1
illustrates an output circuit
101
which is formed in one input/output cell area
100
in a conventional gate array. Each input/output cell area
100
has four NMOS transistors
102
and four PMOS transistors
103
. In
FIG. 1
, the gates of the individual MOS transistors are shown as the NMOS transistors
102
and the PMOS transistors
103
.
The four NMOS transistors
102
are arranged horizontally with respect to the width of the input/output cell area
100
or in the layout direction of a plurality of input/output cell areas
100
. The four PMOS transistors
103
are likewise arranged horizontally with respect to the width of the input/output cell area
100
. The individual NMOS transistors
102
and their associated PMOS transistors
103
are laid out in the height direction of the input/output cell area
100
or in a direction that is perpendicular to the layout direction of the input/output cell area
100
.
As illustrated, an interconnection line
104
is provided to the sources of the two adjoining NMOS transistors
102
. The interconnection line
104
is connected to a power supply line
106
, which is provided above the line
104
and is connected to a low-potential power supply V
SS
. An interconnection line
105
is provided on the sources of the two adjoining PMOS transistors
103
. The interconnection line
105
is connected to a power supply line
107
, which is provided above the line
105
and is connected to a high-potential power supply V
DD
. The drains of the NMOS transistor
102
and PMOS transistor
103
which are associated with each other are connected to external pads (not shown for ease of illustration) via two aluminum interconnection lines
108
.
FIG. 2A
presents a circuit diagram of the output circuit
101
which is formed in the input/output cell area
100
shown in
FIG. 1
, and
FIG. 2B
presents an equivalent circuit diagram of the output circuit
101
expressed in the form of a layout image. Since the four NMOS transistors
102
in
FIG. 1
are connected in parallel, those four transistors are illustrated as a single NMOS transistor
102
in
FIGS. 2A and 2B
. Likewise, since the four PMOS transistors
103
in
FIG. 1
are connected in parallel, those four transistors are expressed as a single PMOS transistor
103
in
FIGS. 2A and 2B
.
In the circuit shown in
FIG. 2B
, when the PMOS transistor
103
turns on and the NMOS transistor
102
turns off in response to an L-level input signal, a charge current I
0H
is supplied to output loads CLU and CLD via an external pad
109
from the high-potential power supply V
DD
. When the PMOS transistor
103
turns off and the NMOS transistor
102
turns on in response to an H-level input signal, on the other hand, a discharge current I
0L
flows in through the external pad
109
from the output loads CLU and CLD.
In such a case where the output circuit is constituted by using the input/output cell area, the size of the input/output cell area
100
is determined through the following three basic steps. First, the number of PMOS and NMOS transistors needed to drive the output loads which are connected to an external pad is determined through a simulation. Secondly, the MOS transistors are laid out while meeting the masking design standards which are used in the exposure process of the MOS transistors. Thirdly, by executing the current analysis at the time the output circuit operates, the width of the aluminum interconnection line is so determined as to secure the electromigration resistance. As pattern miniaturization is increased due to improved process technology, the width CW
0
of each input/output cell area
100
can be made narrower and the layout pitches between a plurality of input/output cell areas are made shorter.
The conventional input/output cell area
100
comprises a single stage of NMOS transistors
102
and a single stage of PMOS transistors
103
. The width W
0
of the aluminum interconnection line
108
has therefore been determined based on direct current (DC) analysis. More specifically, the width W
0
of the aluminum interconnection line has been selected based on the amount of the current flowing in from an external pad
109
when the four NMOS transistors
102
are turned on, or the current flowing out to the external pad
109
when the four PMOS transistors
103
are turned on.
This design scheme suffers from its inability to withstand the electromigration resistance. The line width W
0
is therefore determined based upon the required resistance against a DC current flowing along the aluminum interconnection line
108
on the PMOS transistor
103
. In this respect, the line width W
0
of the aluminum interconnection line
108
is set unnecessarily large. Because the width CW
0
of the input/output cell area is determined based on the number of the aluminum interconnection lines and the width of each line, the reduction of width CW
0
of the input/output cell area is limited. Consequently, the layout pitches between the input/output cell areas may not be reduced as desired, and thus there is a limit to increasing the number of input/output cell areas. This shortcoming hinders the number of external pins that conventional multipin architectures are able to provide.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention relates to a semiconductor device that is designed having reduced common line widths for connection to external pads while sufficiently considering the electromigration resistance, thereby accomplishing a multipin architecture capable of supporting a greater number of external pads.
A semiconductor device according to this invention includes a plurality of cell areas laid out along a periphery of the semiconductor device, and a plurality of transistors formed in each cell area. The transistors in each cell area are classified into at least three transistor groups,which are arranged in a direction perpendicular to the circumferential direction of the semiconductor device. Each of the at least three transistor groups is connected to one of a high-potential power supply and a low-potential power supply. The semiconductor device has at least one line which is common to the transistor group connected to the high-potential power supply and the transistor group connected to the low-potential power supply and serves to connect those transistor groups to external pads.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principals of the invention.
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patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4825107 (1989-04-01), Naganuma et al.
patent: 4992845 (1991-02-01), Arakawa et al.
patent: 4994866 (1991-02-01), Awano
patent: 5087955 (1992-02-01), Futami
patent: 5162893 (1992-11-01), Okano
patent: 5365091 (1994-11-01), Yamagishi
patent: 5552618 (1996-09-01), Taniguchi et al.
patent: 249988 (1987-12-01), None
patent: 563973 (1993-10-01), No
Arent Fox Kintner & Plotkin & Kahn, PLLC
Crane Sara
Fujitsu Limited
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