Method of increasing trench density for semiconductor

Details Method of increasing trench density for semiconductor Method of increasing trench density for semiconductor

1999-11-24

2001-09-18

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S430000, C438S435000

Reexamination Certificate

active

06291310

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor technology, and in particular, to increasing the density of trenches for applications such as power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
Integrated circuit manufacturers continually strive to increase the number of devices that can be formed across a single wafer. Power MOSFETs, due to their required large gate areas, typically occupy the entire area of a die on a semiconductor wafer. In conventional power MOSFETs, these required large gate areas pose a limit on the number of dies that can be realized per wafer(i.e. “die density”). One way to overcome this limit is to form a trench into the wafer and use its recess to form a three-dimensional gate. A three dimensional gate reduces the two-dimensional surface dimensions of a die (i.e. the “die size”) without sacrificing gate area. Power transistors of this type are often referred to in the art as “Power Trench MOSFETs.”
A cross-sectional view of a typical trench MOSFET
10
, which can be used for power applications, is shown in FIG.
1
. It includes an n-type substrate
102
upon which an n-type epitaxial layer (not shown in
FIG. 1
) is typically grown. The substrate
102
embodies the drain of the trench MOSFET
10
. A p-type body layer
108
covers the epitaxial layer. A pair of trenches
100
extend through the body layer
108
and into the epitaxial layer. Dielectric layers
104
are formed on the walls of the trenches
100
. The dielectric layers
104
have inner walls facing towards the centers of their respective trenches
100
and outer walls. N+ source regions
10
flank the outer walls of the dielectric layers
104
and extend into the body layer
108
. Heavy body regions
112
, also within the body layer
108
, are positioned between the source regions
110
. Conductive layers
106
(e.g., polysilicon) substantially fill the trenches
100
and embody the gate of the trench MOSFET
10
. Finally, dielectric caps
114
cover the filled trenches
100
and also partially cover the source regions
110
.
During fabrication of the trench MOSFET
10
an anisotropic etch step is typically performed to form the trenches
100
. An anisotropic etch is used, as opposed to an isotropic etch, since an anisotropic etch etches substantially in one direction, which in this case, is vertical and downward. The substantially vertical trenches
100
help to maintain the width defined by the trench patterns, a characteristic that is beneficial in maintaining a predetermined distance between the centers of the trenches
100
(i.e., trench pitch).
After the trenches
100
are formed, a rounding etch is typically performed to round corners, which form at the top and bottom of the trenches
100
during the trench etch step. Another step that is typically performed just prior to growing the gate oxide for the trench MOSFET
10
, is the growing of a sacrificial oxide, which is grown and then stripped to remove defects from the walls of the trenches.
To increase the trench density, it is desirable to minimize the trench width as well as the trench pitch. However, both of these dimensions are limited by constraints imposed by manufacturing equipment as well as device operational requirements. The minimum reliably manufacturable trench width is generally dictated by the capability of the photolithography equipment. Further, the minimum width of the mesa formed between trenches is defined by the source and heavy body regions and the source contact areas.
What is needed, therefore, is a method that can overcome limitations on the minimum achievable trench width and trench pitch to provide electronic devices, such as trench MOSFETs, with a higher trench density despite limits imposed by minimum lithographic print dimension capabilities, and without violating the minimum allowable mesa width.
SUMMARY OF THE INVENTION
The present invention provides a method of increasing the trench density of a trench MOSFET by reducing the effective pitch between adjacent trenches of a trench MOSFET. Pitch reduction is accomplished by first patterning adjacent trenches so that the mesa between the trenches has a width less than the minimum allowable mesa width. After the trenches are formed, a silicon layer is grown on the walls of the trenches, to a thickness that effectively widens the mesa between adjacent trenches to a width that is greater than or equal to the minimum allowable mesa width. Preferably, the thickness of the silicon layer is selected such that the final width of the mesa approaches the minimum allowable mesa width. By doing this, a maximum reduction in trench pitch can be realized.
In one aspect of the method of the present invention, selective areas (or “trench opening accesses”) of a substrate are defined. Through these trench opening accesses, trenches are formed into the substrate, preferably by using an anisotropic etch. Once the trenches are formed, the trenches are optionally annealed, preferably using hydrogen gas at elevated temperatures and sub-atmospheric pressures so that corners at the tops and bottoms of the trenches become rounded and so that the defect density on the walls of the trenches is reduced. This anneal process is described in commonly-assigned patent application Ser. No. 09/448,884, entitled “Hydrogen Anneal for Creating an Enhanced Trench for Trench MOSFETs.” Finally, a layer of silicon is formed on the trench walls, preferably by epitaxial deposition, to ensure that the mesa width is greater than or equal to the minimum allowable mesa width.
In yet another aspect of the invention, the method of the present invention is used to fabricate a trench MOSFET characterized by a reduced trench pitch. The method comprises the steps of: (i) providing a substrate of a first dopant charge type; (ii) growing a base silicon layer of the same first dopant charge type on the substrate; (iii) forming at least two trenches into the base silicon layer, each trench defined by a first end in a plane defined by a major surface of the substrate and by walls that extend to a second end at a trench-terminating depth into the base silicon layer; (iv) annealing the trenches to (a) reduce the number of defects on the walls of the trenches and (b) round corners at the first and second ends of the trenches; (v) growing a second layer of silicon on the trench walls, preferably by epitaxial deposition, to ensure that the width of the mesa between adjacent trenches of the trench MOSFET is greater than or equal to the minimum allowable mesa width; (vi) growing a dielectric layer over said second layer of silicon; (vii) forming a conductive layer over said dielectric layer, said conductive layer embodying the gate of the trench MOSFET; (viii) patterning and implanting a dopant of a second charge type to form wells interposed between adjacent trenches; and (ix) patterning and implanting a dopant of the first charge type to form regions that embody the source regions of the trench MOSFET.
Other features and advantages of the invention will be apparent from the following detailed description and the drawings.


REFERENCES:
patent: 5268311 (1993-12-01), Euen et al.
patent: 5897360 (1999-04-01), Kawaguchi
patent: 5906680 (1999-05-01), Meyerson

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