Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1999-09-15
2001-08-07
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S686000, C257S723000, C257S685000, C110S10400A, 36
Reexamination Certificate
active
06271587
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to circuits constructed from stacks of identical chips, and more particularly, to a method for providing chip enablement signals that does not require alterations in the chips.
BACKGROUND OF THE INVENTION
Consider a circuit such as a computer memory that is constructed from layers of planar arrays of memory cells that are stacked to form a 3-dimensional memory. The layers may be individual integrated circuit chips or traditional circuit boards. The layers are typically connected by a number of vertical connect lines. Typically, there is an address associated with each layer and an enablement line that connects that layer to one or more of the vertical connect lines when the cells thereon are being selected.
There are two basic methods for selecting a layer. In the first method, the address of the selected layer can be communicated on a subset of the vertical connect lines and be decoded on the layer. The decoded address is then compared to an address stored on the layer, and if the addresses match, the enablement line is energized. This method requires that each layer be programmed with its specific address prior to being connected in the stack. Hence, the layers are not identical. In addition, the ROM needed to store the address may require a different fabrication technology than the remaining circuitry on the layer. This is particularly important in the cases in which the layers are individual semiconductor chips, since mixing devices constructed with different fabrication processes is not always possible.
The second method places the decoding circuitry on a different layer. In this case, each layer must have an enablement connection in the vertical connect lines. The vertical connected select lines must be distinct and each layer must “know” which line corresponds to that layer while being identical to every other layer. No prior art solution to this problem is known that does not require programming bits on each layer to make that layer unique.
Broadly, it is the object of the present invention to provide an improved layer select arrangement in a circuit constructed from a plurality of identical circuit layers.
It is a further object of the present invention to provide a layer select method that does not require each layer to be separately programmed with an address.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit having first and second identical layers of circuitry. Each layer includes a substrate having a plurality of components thereon. Each layer also includes circuit selection circuitry for enabling the integrated circuit components on that layer to perform a predetermined function. The circuit selection circuitry includes a circuit selection terminal for receiving a signal that enables the predetermined function. Each layer also includes N input pads and N output pads, where N>1. The input and output pads are labeled from 1 to N. Each input pad is connected to a corresponding one of the output pads. The connection scheme is chosen such that there is a one-to-one mapping between the input pads and the output pads and no input pad is connected to an output pad on that layer having the same label as the input pad. The circuit selection terminal is connected to a predetermined one of the input pads. The layers are connected such that the input pad labeled k on the second layer is connected to the output pad labeled k on the first layer for k=1 to N.
REFERENCES:
patent: 5261115 (1993-11-01), Saunders et al.
Thai Luan
Tran Minh Loan
Ward Calvin B.
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