Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Phase comparison
Reexamination Certificate
1999-02-16
2001-09-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Phase comparison
C375S371000, C375S373000, C702S072000
Reexamination Certificate
active
06291979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for and a method of detecting a delay fault in a phase-locked loop circuit, and more particularly, relates to a delay fault detecting apparatus and a delay fault detecting method which are suitable for detecting delay faults in phase-locked loop (hereinafter referred to as PLL) circuits formed on VLSI (very large scale integrated circuit) chips respectively.
2. Description of the Related Art
A synchronous system performs a cooperative operation by sharing a timing of a clock edge with one another. The more the timing of the shared edge is controlled at high accuracy, the more the synchronous system can operate at a high rate.
FIG. 1
shows an example of the synchronous system. This system has such a configuration that a plurality of (in this example, two) VLSI chips
11
and
12
are placed on a single board (not shown). A reference clock &phgr; is supplied to each of the VLSI chips
11
and
12
from a high precision oscillator (for example, a crystal-based clock generator)
13
provided on the board. PLL circuits
14
and
15
on those VLSI chips output, as shown in
FIG. 2
, clocks &phgr;
11
, &phgr;
12
, and &phgr;
21
, &phgr;
22
generated by the on-chip clock generators with their edges synchronized with the edge of the reference clock &phgr; supplied from the outside, and those clocks are distributed to subsystems
16
and
17
, respectively. (For example, refer to a reference literature d1.)
As stated above, by synchronizing the edge of an internal clock with respect to the edge of a reference clock, data can be transmitted and received between different chips. The PLL circuits
14
and
15
play a role in minimizing a clock skew and ensuring a high speed operation of the system, by aligning the frequency and the phase of an oscillation waveform of a voltage-controlled oscillator (hereinafter referred to as VCO) with respect to the frequency and the phase of the inputted reference clock &phgr;.
As is well known, in a microcomputer, an instantaneous value (a peak-to-peak jitter or the like) of the worst case may determine the operational frequency of the microcomputer. Therefore, it is necessary in the microcomputer to positively detect, by a test, any fault that increases a clock skew even for an instant.
Next, an influence of a delay fault in a PLL circuit on a system will be discussed.
FIG. 3
shows an example of the PLL circuit. This PLL circuit comprises a phase-frequency detector
21
, a charge pump circuit
22
, a loop filter
23
, a VCO
24
, and a clock decode and buffer circuit
25
. Now, it is assumed that a delay fault DF
1
is present at the reference clock input side of the phase-frequency detector
21
. As shown in
FIG. 4
, a reference clock &phgr;
REF
(indicated by a solid line) applied to the phase-frequency detector
21
of the PLL circuit becomes a clock &phgr; (indicated by a dotted line) which has been delayed by a constant time interval due to the delay fault DF
1
present at the input side, and the delayed clock &phgr; is fed into the charge pump circuit
22
at the next stage. In the PLL circuit, an edge of an internal clock &phgr;
1
(indicated by a solid line) outputted from the clock decode and buffer circuit
25
is synchronized with respect to the edge of the dotted line clock &phgr; which has been delayed by the constant time interval. As a result, a clock skew occurs in response to the delay fault DF
1
. Moreover, the clock skew, which is a deviation generated at the reference clock input side, is not compensated in the PLL circuit and remains as a constant value. As a result, it appears that a large steady-state deviation remains.
Since this delay fault DF
1
is not a fault of an internal block (internal component) of the PLL circuit, the PLL circuit gets into a synchronous state. Accordingly, it is difficult to detect a delay fault at the reference clock input side even if internal blocks of the PLL circuit are tested. However, a delay fault of this type can easily be detected by comparing the external reference clock &phgr;
REF
with the internal clock &phgr;
1
.
Next, as shown in
FIG. 5
, it is assumed that a delay fault DF
2
is present at the Up signal input side of the charge pump circuit
22
. Due to the delay fault DF
2
, a timing in the charge pump circuit
22
for converting an Up signal inputted thereto from the phase-frequency detector
21
to an analog signal to output the analog signal is delayed. Further, the delay of the analog signal causes a timing of an oscillation waveform of the VCO
24
to delay.
In the next step, the phase-frequency detector
21
compares the edge of the reference clock &phgr;
REF
with the edge of the internal clock &phgr;
1
, and controls the timing of the oscillation waveform of the VCO
24
by using, as a phase error signal, a time interval between the rising edges of the two clocks. The control for the feedback loop is carried out until the rising edges of both the clocks are aligned with each other. Therefore, the delay fault DF
2
appears simultaneously with a state transition and is compensated by the feedback. The delay time has its maximum value when the state transition occurs. Consequently, as shown in
FIG. 6
, a clock slew has also its maximum value when the state transition occurs, and it is decreased to zero with the lapse of time. In this manner, since a PLL circuit is a feedback system, a transient skew occurs. A timing at which a transient skew occurs is limited, and hence it is difficult to detect the transient skew by a test.
As mentioned above, in the case that a delay fault DF
1
is present at the reference clock input end of the phase-frequency detector
21
, a clock skew having a constant time interval occurs. This clock skew is not compensated in the PLL circuit. On the other hand, in the case that a delay fault DF
2
is present at the Up signal input end of the charge pump circuit
22
, a large clock skew transiently appears in correspondence to a state transition shown in FIG.
7
. This transient clock skew DF
2
is compensated in the PLL circuit and approaches toward zero. All the delay faults of other blocks (an input end of the loop filter
23
and an input end of the VCO
24
) of the PLL circuit can be mapped to the delay fault in the input end of the charge pump circuit
22
.
A stuck-at fault testing (for example, refer to a reference literature d2) has conventionally been utilized most widely in the verification test and the manufacturing test of VLSI chips. First, the stuck-at fault testing will briefly be explained.
A fault model is a model in which a physical defect is abstracted. When the fault model is used, a fault can easily be simulated using a computer. For example, a state in which an output of a CMOS (complementary metal-oxide semiconductor) inverter keeps taking a logical value “1” can be explained by using a model in which a stuck-at 1 fault is present at the output of the inverter. As a cause of this type of fault, there can be considered a defect that a short circuit has been formed between the output of the inverter and a power supply voltage V
DD
or a physical defect that a drain of an nMOS (n-channel metal-oxide semiconductor) has been opened.
In the testing, a test pattern is applied to primary inputs of a circuit under test and a response pattern of the circuit appearing at primary outputs of the circuit under test is observed. A check is made, by comparing this response pattern with an expected value pattern in fault-free operation, to see whether the circuit is faulty or not.
FIG. 8
shows a combinational circuit of a NAND gate ND
1
having a stuck-at 0 fault and a NAND gate ND
2
having no stuck-at fault. The outputs of both the NAND gates ND
1
and ND
2
are taken out through an OR gate OR
1
as a primary output.
A test pattern which can detect the stuck-at 0 fault in this combinational circuit is “110”. That is, it means that as shown in
FIG. 8
, the test pattern “110” is applied to the primary inputs of the combinational circuit. The
Ishida Masahiro
Soma Mani
Yamaguchi Takahiro
Advantest Corporation
Gallagher & Lathrop
Lathrop David N.
Metjahic Safet
Nguyen Vincent Q.
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