Multiple power source electrostatic discharge protection...

Details Multiple power source electrostatic discharge protection... Multiple power source electrostatic discharge protection...

2000-01-21

2001-09-18

Tso, Edward H. (Department: 2838)

Electricity: battery or capacitor charging or discharging

Serially connected batteries or cells

With discharge of cells or batteries

Reexamination Certificate

active

06291964

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to a multiple power source ESD protection circuit that operates through charge coupling.
2. Description of the Related Art
Failure of integrated circuit (IC) such as dynamic random access memory (DRAM) or static random access memory (SRAM) is often caused by electrostatic discharge during manufacturing or subsequent handling. For example, several hundred to several thousand volts can be generated when a person walks over a carpet, even if the surrounding relative humidity is high. When the relative humidity is low, more than ten thousand volts can be generated. If the electrified person touches a product chip, static electricity may suddenly discharge through the chip and result in chip failure. Hence, to prevent damages to silicon chip due to electrostatic discharge, various circuit protection methods are developed. The most common method of protecting against ESD is to install an on-chip ESD protection circuit between a bonding pad and connected internal circuit.
Since thickness of a gate oxide layer is reduced with an increase in the level of integration. the gate oxide layer will break down at the breakdown voltage at the source/drain junction or even lower. Under such circumstances, effectiveness of the original ESD protection circuit is greatly compromised. In addition, internal circuits are generally designed according to minimum design rules. The ESD protection circuit is not designed to withstand the large transient current produced in an electrostatic discharge (because sufficient separation must be allowed from a contact to the edge of the diffusion region and the gate region). Thus, high-level integrated circuits on a silicon chips are exceptionally vulnerable to electrostatic discharge. Consequently, ESD is one of the leading causes of failure in deep-submicron devices.
A conventional charge-coupled ESD protection circuit utilizes the coupled charges in an electrostatic discharge to increase the voltage in a floating gate and trigger the opening of a parasitic diode. Ultimately, the sudden current surge due to ESD is channeled away and the internal circuit inside the silicon chip is protected. However, due to the presence of a parasitic diode, effectiveness of the positive voltage stress to ground line Vss and the negative voltage stress to voltage source Vdd type of conventional charge-coupled ESD protection circuit is diminished.
FIG. 1
is a schematic diagram of a conventional ESD charge-coupled protection circuit. As shown in
FIG. 1
, the ESD charge-coupled protection circuit
10
is installed between a bonding pad
12
and an internal circuit
14
. The protection circuit
10
includes two N-type metal-oxide-semiconductor (NMOS) transistors
16
and
18
and two P-type metal-oxide-semiconductor (PMOS) transistors
20
and
22
. The source terminal of the NMOS transistor
16
is grounded (via a ground line Vss); the gate terminal is connected to the drain terminal of the NMOS transistor
18
; and the source terminal is connected to the bonding pad
12
. The source terminal of the NMOS transistor
18
is connected to the ground line Vss and the gate terminal is connected to a voltage source Vdd. The source terminal of the PMOS transistor
20
is connected to the voltage source Vdd; the gate terminal is connected to the drain terminal of the PMOS transistor
22
; and the drain terminal is connected to the bonding pad
12
. The source terminal of the PMOS transistor
22
is connected to the voltage source Vdd and the gate terminal is connected to the ground line Vss.
In normal operation, the gate terminal of the NMOS transistor
18
and the gate terminal of the PMOS transistor
22
are connected to the voltage source Vdd and the ground line Vss, respectively. Hence, both transistors
18
and
22
are turned on. The gate of the NMOS transistor
16
and the gate of the PMOS transistor
20
are in a non-floating state. Hence, both transistors
16
and
20
are turned off. Under such circumstances, there is no charge coupling.
When there is electrostatic discharge (ESD), using a positive stress as an example, since the voltage source Vdd is in a floating state (an abnormal operating condition), the NMOS transistor
18
is turned off. Within a very short time, the gate terminal is in a floating state. Hence, the positive stress voltage applied to the bonding pad
12
couples with the gate terminal of the NMOS transistor
16
through a parasitic capacitor
24
between the drain and the gate terminal of the NMOS transistor
16
. The coupling of the parasitic capacitor
24
triggers the NMOS transistor
16
so that the positive stress voltage is discharged through a ground line Vss via the NMOS transistor
16
.
Due to the forward bias of the parasitic diode
26
of the PMOS transistor
20
, a positive stress voltage applied to the bonding pad
12
is fed back to the gate terminal of the NMOS transistor
18
via the parasitic diode
26
and the voltage source Vdd. Hence, the NMOS transistor
18
is turned on. Therefore, the degree of charge coupling decreases and the capacity for ESD protection deteriorates. Similarly, a negative stress voltage applied to the bonding pad
12
is fed back to the voltage source Vdd.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a multiple power source ESD protection circuit between a bonding pad and an internal circuit that has a higher circuit protection capacity than a conventional circuit.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a multiple power source electrostatic discharge (ESD) protection circuit. The ESD protection circuit is installed between a bonding pad and an internal circuit. The FSD protection circuit includes five NMOS transistors and a PMOS transistor. The source terminal of a first NMOS transistor is grounded and the drain terminal of the first NMOS transistor is connected to a bonding pad. The drain terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor, and the gate terminal of the second NMOS transistor is connected to a first voltage source. The drain terminal of the third NMOS transistor is connected to the source terminal of the second NMOS transistor the gate terminal of the third NMOS transistor is connected to a second voltage source and the drain terminal of the third NMOS transistor is grounded. The drain terminal of the fourth NMOS transistor is connected to a voltage source pad and the gate terminal of the fourth NMOS transistor is connected to the first voltage source. The drain terminal of the fifth NMOS transistor is connected to the source terminal of the fourth NMOS transistor and the gate terminal of the fifth NMOS transistor is connected to the second voltage source. The source terminal of the PMOS transistor is connected to the voltage source pad, the gate terminal of the PMOS transistor is connected to source terminal of the fifth NMOS transistor and the drain terminal of the PMOS transistor is connected to the bonding pad. The voltage source pad is connected to either the first voltage source or the second voltage source.
The multiple power source ESD protection circuit of this invention has a higher circuit protection capacity than a conventional circuit. This is because whether a positive voltage stress is applied to ground or a negative voltage stress is applied to the voltage source pad, the parasitic diode of both the PMOS transistor and the first NMOS transistor is not affected by the actual states at their gate terminals. In fact, the gate terminals of both the first NMOS transistor and the PMOS transistor are in a floating state. The charge-coupling capacity of the parasitic capacitors between the drain terminal and the gate terminal of both the first NMOS transistor and the PMOS transistor can be utilize

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