Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-11-10
2001-08-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S142000, C331S00100A, C375S376000
Reexamination Certificate
active
06278303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device incorporating a synchronizing clock generation circuit generating an internal dock signal in synchronization with an externally applied clock signal.
2. Description of the Background Art
Some conventional semiconductor devices incorporate a circuit that generates an internal clock signal in synchronization with an externally applied clock signal, for example, a PLL (Phase Locked Loop) circuit.
FIG. 17
schematically shows a structure of a conventional semiconductor device
500
.
Referring to
FIG. 17
, semiconductor device
500
includes a PLL circuit
554
receiving clock signals REF.CLK and FB.CLK to generate a clock signal ICLK, a clock driver
560
amplifying and providing a clock signal CLK, and an internal circuit
562
receiving the output clock of clock driver
560
to carry out a predetermined operation.
Internal circuit
562
includes a latch circuit
566
having a plurality of flipflop circuits receiving a clock signal for operation, and a combination circuit
564
which is an internal circuit other than the latch circuit.
In such large scale integrated circuits (LSI), a latch circuit is connected including a plurality of flipflop circuits and the like at the output of the clock driver.
The operation of PLL circuit
554
will be described briefly hereinafter. PLL circuit
554
outputs a clock signal ICLK so that clock signal FB.CLK that is fed back is in synchronization and in equal phase with externally applied clock signal REF.CLK. As a result, clock signal ICLK in phase with clock signal REF.CLK is applied to internal latch circuit
566
.
By this structure, synchronization can be established between internal and external clock signals of the LSI.
In general, the LSI has a great amount of power consumed in the circuitry that distributes the clock signal. A circuit that distributes a clock signal includes, for example, a clock driver to drive a clock interconnection of great interconnection capacitance and load capacitance.
In the LSI used in portable equipment, a period in which there is no input signal to be processed, i.e. the standby period, occupies the major portion. It is often not necessary to operate the main function of the LSI during the standby period. Power consumption can be reduced significantly if the clock can be suppressed during the standby period.
Conventional problems set forth in the following are noted when the circuit operation is suppressed temporarily for the purpose of reducing power consumption.
In the circuit shown in
FIG. 17
, the possible method to cease the clock signal is to provide a switch between PLL circuit
554
and clock driver
564
to suppress clock generation of PLL circuit
554
, whereby the operation of clock driver
560
is suppressed. This method is disadvantageous in that, when generation of the clock signal is recommended and applied to internal circuit
562
, there will be a period of time in which synchronization cannot be established between clock signal ICLK generated from PLL circuit
554
and clock signal REF.CLK.
There is a possibility that the data stored in latch circuit
566
will be damaged by the unstable clock signal applied to internal circuit
562
until synchronization of the clock signal is established, resulting in erroneous operation.
Thus, there was a problem that the data in the internal latch circuit will be damaged due to the period of time required for synchronization of the PLL at the restart of the clock in the conventional method. To this end, the invention disclosed in Japanese Patent Laying-Open No. 7-202687 was conceived.
FIG. 18
shows a circuit diagram of a clock circuit
400
disclosed in Japanese Patent Laying-Open No. 7-202687.
Referring to
FIG. 18
, clock circuit
400
includes a phase difference voltage conversion circuit PVC receiving an external clock signal CLK and a feed back clock signal FCK, a voltage control oscillation circuit VCO under control of the output voltage of phase difference voltage conversion circuit PVC to output a common clock signal, a clock supply circuit CS receiving the output of voltage control oscillation circuit VCO to supply a local clock signal LCK to a logic circuit LD, a dummy clock circuit DCS receiving the output of voltage control oscillation circuit VCO to output a dummy clock signal DCL, and a select circuit SEL receiving a control signal R according to an operation mode MODE to apply either local clock signal CLK or dummy clock signal DCL to phase difference voltage conversion circuit PVC as feed back clock signal FCK.
However, the circuit shown in
FIG. 18
was disadvantageous in that phase difference occurs between external clock signal CLK and local clock LCK by select circuit SEL.
FIG. 19
is an operation waveform diagram to describe the operation of clock signal
400
of FIG.
18
.
At time t0-t1, the operation mode corresponds to an active state. Synchronization is established between external clock signal CLK and local clock signal LCK.
At time t1-t2, the operation mode changes from the active state to the standby state. In response, local clock signal LCK is fixed at an L level (logical low) during the period of time t2-t3.
At time t3-t4, the operation mode changes again from the standby state to the active state. In response, local clock LCK is in synchronization with external clock signal CLK at time t4 and et seq.
As to the locking state of the external clock signal and the local clock signal in the vicinity of time to, a phase comparator PD of phase difference voltage conversion circuit PVC is at a steady state when input signals CK
1
and CK
2
are in phase. When clock circuit
400
is at a steady state, feed back clock signal FCK is in phase with external clock signal CLK.
Feed back clock signal FCK corresponds to the output of local clock signal LCK supplied to logic circuit LD via select circuit SEL. Therefore, local clock signal LCK leads external clock signal CLK in phase by an offset time TOF corresponding to the delay time by select circuit SEL.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device including a clock supply circuit absent of phase difference between an external clock signal and a clock signal applied in an internal circuit in an active state, and that can return from a standby state without damaging data stored in the latch circuit while suppressing power consumption by ceasing the clock signal in a standby state.
According to an aspect of the present invention, a semiconductor device includes a synchronizing clock generation circuit, a clock supply circuit, a clock transmission unit, and an internal circuit.
The synchronizing clock generation circuit generates a source clock signal in synchronization with an external clock signal. The synchronizing clock generation circuit includes a clock delay circuit delaying the source clock signal to output a feed back clock signal, and a signal generation circuit generating a source clock signal according to the phase difference between an external clock signal and a feed back clock signal when in an active mode and a standby mode of the operation mode.
The clock supply circuit receives the source clock signal to output an intermediate clock signal in an active mode and to render the output inactive in a standby mode.
The clock transmission unit transmits the intermediate clock signal. The internal circuit receives an internal clock signal corresponding to the intermediate clock signal from the clock transmission unit to carry out a predetermined operation. The internal circuit includes a data retain circuit receiving and retaining data according to the internal clock signal.
According to another aspect of the present invention, a semiconductor device includes a synchronizing clock generation circuit, a clock supply circuit, a clock transmission unit, an internal circuit, a main power supply line, and a sub power supply line.
The synchronizing clock generation circuit
Makino Hiroshi
Nakanishi Jingo
Yoshimura Tsutomu
Cunningham Terry D.
Luu An T.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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