Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-02-18
2001-06-26
Reichard, Dean A. (Department: 2831)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S306200, C361S309000, C361S310000, C361S782000
Reexamination Certificate
active
06252177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to capacitor mounting structures for capacitors of multilayer printed circuit boards, and more particularly to a low inductance capacitor mounting structure.
2. Description of the Related Art
As operating speeds and current densities increase for digital systems, noise has become an increasingly important concern. One source of high-frequency noise in digital systems is the parasitic inductance of a capacitor mounting structure for capacitors of printed circuit boards in such systems. One source of parasitic inductance has been the specific region bounded and defined by a bottom surface of a capacitor, a capacitor surface or solder pad, and vias of a capacitor mounting structure. This type of parasitic inductance is described in Stoddard, commonly-owned U.S. Pat. Nos. 5,375,035 and 5,459,642, of which Applicant in inventor. Other regions of a capacitor mounting structure, however, continue to provide parasitic inductance.
Certain of these regions are associated with the vias of a capacitor mounting structure. A via is an electrically conductive path through a substrate dielectric layer which connects solder pads to a power or ground conductor plane of a printed circuit board. When current is provided through the vias, the vias produce a magnetic filed forming a magnetic circuit around the vias. So far as is known, conventional efforts to reduce inductance of these regions have been unsuccessful. Such efforts have included either increasing the diameter of vias or providing a capacitor terminal for each via. Another approach to minimizing capacitor inductance has been to confine the magnetic field within a capacitor. This approach, however, has typically included providing vias outside the area where soldering occurs to avoid placing solder within a via. Traces between the capacitor body and the vias have provided a high inductance.
Further, another region providing parasitic inductance is associated with the capacitor body and the solder pads. The high inductance of certain regions of a capacitor mounting structure has inhibited capacitor response at high frequencies and caused retention of noise in printed circuit boards.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a low inductance capacitor mounting structure for capacitors of multilayer printed circuit boards. The capacitor mounting structure includes pads onto which a capacitor is mounted and vias or slots for connecting the solder pads to an upper conductor plane and a lower conductor plane. In the mounting structure, current is carried across the width of the solder pads so that a current in the solder pads flows directly underneath the current in the capacitor. This confinement of the magnetic field which is between the capacitor and solder pads reduces the inductance of the associated magnetic path. The mounting structure also provides the lower conductor plane slightly below the upper conductor plane. The close spacing of the conductor planes confines a magnetic field, which is around the set of via segments between the two conductor planes, so as to reduce inductance of the associated magnetic path. The close spacing also provides return paths between the lower conductor plane and the upper conductor plane with displacement current across spaces formed between the upper conductor plane and the lower conductor plane near the vias or slots between the two planes. These return paths substantially reduce inductance between the upper and lower conductor planes, thereby reducing the impedance of critical structures in the printed circuit board such as the power distribution structure of the printed circuit board. The reduced inductance of the capacitor mounting structure achieved b reducing the inductance of these regions improves the effectiveness of the associated capacitor, minimizes the undesirable retention of high-frequency noise by the associated printed circuit board, and allows for a low impedance characteristic for printed circuit boards.
REFERENCES:
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patent: 5375035 (1994-12-01), Stoddard
patent: 5459642 (1995-10-01), Stoddard
patent: 6020562 (2000-02-01), Burns et al.
Sisler, John, “Eliminating Capacitors From Multilayer PCBs,” reprinted from Printed Circuit Design vol. 8, No. 7, Jul. 1991, 7 pages.
Ramo, Simon, et al., Fields and Waves in Communications Electronics, Second Edition, Copyright©1965, 1984 by John Wiley & Sons, Inc., pp. 79-81.
European Serach Report, The Hague, Jun. 14, 1994, 3 pages.
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Patent Abstracts of Japan, vol. 16, No. 554 (E-1293) Nov. 25, 1992 & JP-A-04 211 191 (Hitachi Ltd.) Aug. 3, 1992.
Akin Gump Strauss Hauer & Feld & LLP
Compaq Computer Corporation
Ngo Hung V
Reichard Dean A.
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