Precision trim circuit for delay lines

Details Precision trim circuit for delay lines Precision trim circuit for delay lines

1998-06-22

2001-03-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000

Reexamination Certificate

active

06204710

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to trim circuits for delay lines. More specifically, the invention relates to a trim circuit that responds to environmental and process variations in a manner similar to an associated delay line.
BACKGROUND OF THE INVENTION
Delay lines are used in digital circuits such as board-level systems and integrated circuit (IC) devices, including field programmable gate arrays (FPGAS) and microprocessors, to control the timing of various signals in the digital circuits. A simple delay line receives an input signal on an input terminal and provides an output signal on an output terminal that is a copy of the input signal delayed by a certain time period (referred to as the delay D of the delay line). More complicated delay lines are tuneable so that delay D of the delay line can be adjusted.
An IC device such as an FPGA can use a tuneable delay line to synchronize clock signals in various parts of the FPGA. As shown in
FIG. 1
, an FPGA
100
comprises a delay line
110
, configurable logic circuits
120
, and configurable logic circuits
130
. Clock signal CLK
1
is provided to an input terminal of delay line
110
and to the clocked circuits (not shown) of configurable logic circuits
120
. Delay line
110
drives a clock signal CLK
2
to configurable logic circuits
130
. Before clock signal CLK
2
reaches configurable logic circuits
130
, clock signal CLK
2
may be skewed by various factors such as capacitance, heavy loading on the clock line, and propagation delay. The various skewing factors are represented by clock skew
140
, which causes a skew delay S_D (not shown) on clock signal CLK
2
. To distinguish clock signal CLK
2
from the skewed version of clock signal CLK
2
, the skewed version is referred to as skewed clock signal S_CLK
2
. Skewed clock signal S_CLK
2
drives the clock input terminals (not shown) of the clocked circuits within configurable logic circuits
130
. For proper operation of FPGA
100
, skewed clock signal S_CLK
2
should be synchronized with clock signal CLK
1
. Skewed clock signal S_CLK
2
can be synchronized with clock signal CLK
1
by adjusting delay line
110
so that delay D plus skew delay S_D is equal to a multiple of the period of clock signal CLK
1
. Various circuits and methods of using delay lines to synchronize clock signals are well known in the art.
FIG. 2
shows a block diagram of a conventional tuneable delay line
200
. Tuneable delay line
200
comprises a plurality of delay elements
210
_
1
to
210
_N and a multiplexer
220
. Delay elements
210
_
1
to
210
_N are coupled in series so that the input terminal of a delay element
210
_X is coupled to the output terminal of a delay element
210
_X−1, where X is an integer from
2
to N. The input terminal of delay element
210
—
1 is coupled to input terminal IN of tuneable delay line
200
. Each delay element
210
_X drives a delayed output signal D_O[X]. Delayed output signal D_O[
0
] is provided by the input terminal of delay element
210
_
1
. Each delay element is identical and provides a delay equal to base delay B_D. Thus, each delayed output signal D_O[X] is delayed by base delay B_D from the previous delayed output signal D_O[X−1].
Therefore, each delayed output signal is a copy of input signal IN delayed by some multiple of basic delay B_D of tuneable delay line
200
. Specifically, delayed output signal D_O[
0
] is a copy of input signal IN delayed by zero times basic delay B_D, (i.e. not delayed). Delayed output signal D_O[
1
] is a copy of input signal IN delayed by basic delay B_D. Delay output signal D_O[
2
] is a copy of input signal IN delayed by two times basic delay B_D. In general, delayed output signal D_O[X] is a copy of input signal IN delayed by X times the basic delay B_D.
Multiplexer
220
receives some or all of the delayed output signals. Thus, the input terminals of multiplexer
220
are coupled to the delay elements. Multiplexer
220
is controlled by delay select signals DS[
0
-M]. To avoid confusion, terminals are referred to with the same identifier as the signals driven by the terminal. For example, delayed output signal D_O[
2
] is driven by output terminal D_O[
2
]. As used herein, signals that logically form groups are referred to using brackets and a number for each signal. If more than one signal is referred to simultaneously, brackets containing a range of numbers are used. For example, delay select signals DS[
0
-M] comprise M+1 signals that are referred to as DS[
0
], DS[
1
], . . . DS[M]. Delay select lines DS[
0
-M] select which delayed output signal multiplexer
220
drives on output terminal OUT.
Thus, the precision of typical delay lines is base delay B_D. To increase the precision of a delay line, base delay B_D can be decreased. However, with a smaller base delay the delay line must include many more delay elements to be able to provide large delays, which increases the cost of the delay line. Another method to increase the precision of a delay line is to use a trim circuit
310
(
FIG. 3
) with tuneable delay line
200
. Specifically, output signal OUT of tuneable delay line
200
is coupled to the input terminal T_IN of trim circuit
310
. Trim circuit
310
drives a trim output signal T_OUT that is delayed by a trim delay T_D, which is a fraction of base delay B_D. The amount of trim delay T_D is controlled by trim select signals TS[
0
-P].
FIG. 4
is a block diagram of a conventional trim circuit
310
comprising delay elements
410
,
420
,
430
and a multiplexer
450
. Delay elements
410
,
420
, and
430
receive trim input signal T_IN and generate trim delayed output signals TDO[
1
], TDO[
2
], and TDO[
3
], respectively. Multiplexer
450
receives trim input signal T_IN and trim delayed output signals TDO[
1
-
3
]. Multiplexer
450
provides one of the trim delayed output signals TDO[
1
-
3
] or trim input signal T_IN as trim output signal T_OUT, in response to trim select signals TS[
0
-
1
]. Delay element
410
provides a trim delay equal to one-fourth times base delay B_D. Delay element
420
provides a trim delay equal to one-half times base delay B_D. Delay element
430
provides a trim delay equal to three-fourths times base delay B_D. Thus, trim circuit
310
can be configured to provide a trim delay of 0, ¼, ½, or ¾ times base delay B_D. Therefore, the combination of tuneable delay line
200
and the example trim circuit
310
in
FIG. 4
has an effective precision of ¼ times base delay B_D.
To create delays smaller than base delay B_D, the delay elements in trim circuits (e.g., delay elements
410
,
420
,
430
) typically use components that are significantly smaller and faster than the components used in the delay elements of tuneable delay line
200
. However, the speeds of the smaller components are more greatly affected by process variations and environmental conditions than the speeds of the larger components. Thus, the accuracy of conventional trim circuits varies due to process variations and environmental conditions. Therefore, there is a need for a trim circuit for a tuneable delay line that reacts to process variations and varying environmental conditions in a manner similar to the tuneable delay line.
SUMMARY OF THE INVENTION
The invention provides a trim circuit that generates trim delays equal to or greater than the base delay of the tuneable delay line. Thus, the trim circuit and the tuneable delay line can be formed using components of similar sizes. Consequently, the precision trim circuit reacts to process variations and environmental conditions in a manner similar to the tuneable delay line.
In some embodiments of the present invention, a trim circuit comprises a first delay element having a delay greater than or equal to the base delay of the tuneable delay line. The trim ci

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