Boots – shoes – and leggings
Patent
1995-05-04
1996-01-02
Eng, David Y.
Boots, shoes, and leggings
3649371, 3642580, G06F 9302
Patent
active
054816866
ABSTRACT:
A floating-point processor comprises an input format converter, operand registers, a mode selector, an execution unit, and a result format converter. Inputs to the processor include first and second source values, low and high order result precision selectors, and an operation selector. The input format converter converts the source values to extended precision operands for storage in the registers. The mode selector is responsive to the apparent precisions, i.e., the numbers of trailing zeroes in the mantissas, of the operands as well as to the requested precision. The maximum of the requested result precision and the apparent precision determines the precision implemented by the execution unit. The results are stored in extended precision regardless of the execution precision. If the requested precision is less than extended, the result format converter converts the result to the requested format.
REFERENCES:
patent: 4484259 (1984-11-01), Palmer
patent: 5027272 (1991-06-01), Samuels
"IEEE Standard for Binary Floating-Point Arithmetic," ANSI/IEEE Std 754-1985, published by the Institute of Electrical and Electronics Engineers, Inc., N.Y. 1985
Anderson Clifton L.
Eng David Y.
VLSI Technology Inc.
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