RISC microprocessor architecture implementing fast trap and exce

Details RISC microprocessor architecture implementing fast trap and exce RISC microprocessor architecture implementing fast trap and exce

1994-11-21

1996-01-02

Eng, David Y.

Boots, shoes, and leggings

364941, 3642412, G06F 938, G06F 940

Patent

active

054816858

ABSTRACT:
Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.

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