Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1997-11-19
2001-05-22
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120
Reexamination Certificate
active
06236222
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit (IC) devices and, more particularly, to methods and apparatus for detecting misalignments in semiconductor interconnect structures.
2. Description of the Related Art
Currently, in order to remain competitive in the IC industry, IC designers must continuously reduce the overall size and the corresponding cost of IC devices. Thus, IC device features continue to shrink. As a result of this trend toward smaller feature sizes, layer-to-layer alignment is becoming more important to the performance integrity of the IC device. That is, the ability to detect layer-to-layer misalignment is critical since even small misalignments can cause, for example, unintended open circuits between conductive layers, or short circuits between adjacent features on the same layer.
FIG. 1
is a cross section view of a semiconductor device having a plurality of conventionally fabricated layers. IC devices, such as transistors are generally formed on a silicon substrate, and then interconnected to subsequently formed metallization layers with conductive vias. As shown, a base oxide
118
(e.g., SiO
2
) is deposited over the silicon substrate. Next, a lower patterned metallization layer
112
is deposited and patterned over the base oxide
118
to form a lower level of interconnect lines. A lower network of vias
117
is patterned in the base oxide
118
before the lower patterned metallization layer
112
is formed to provide interconnection between the substrate and the lower patterned metallization layer
112
.
A dielectric layer
116
is then formed over the lower patterned metallization layer
112
. An upper network of vias
114
are patterned in the dielectric
116
. Then, an upper patterned metallization layer
110
is deposited and patterned over the dielectric layer
116
. The upper network of vias
114
provides interconnection between the lower patterned metallization layer
112
and the upper patterned metallization layer
110
. The process may then be repeated to form a plurality of patterned metallization layers, via networks, and dielectric layers as needed for a particular application.
The dielectric and patterned metallization layers are typically patterned using well known photolithography techniques. Patterning is typically accomplished by depositing a photoresist layer over the layer to be patterned, and then selectively exposing the photoresist to light through a patterned reticle. Once exposed, the photoresist is developed to form a photoresist mask that is used in etching layers that are exposed and not covered by the photoresist material.
Although the above process usually results in acceptable electrical connections between the substrate and the upper patterned metallization layer
110
, sometimes a faulty connection or open circuit occurs between the substrate and the upper patterned metallization layer
110
occurs. An example of an acceptable connection between the substrate and a first upper feature
110
a
of the upper patterned metallization layer
110
is shown in FIG.
1
. The first upper feature
110
a
is connected through a first upper conductive via
114
a
to a first lower feature
112
a
of the lower patterned metallization layer
112
. The first lower feature
112
a
is connected through a first lower conductive via
117
a
to the substrate. Most importantly, the first upper feature
110
a
, the first upper conductive via
114
a
, the first lower feature
112
a
, and the first lower conductive via
117
a
are substantially aligned along the same first vertical axis
120
. This alignment results in an acceptable electrical interconnection between the first upper feature
110
a
and the substrate.
In contrast, an example of a clearly unacceptable connection between the substrate and a second upper feature
110
b
of the upper patterned metallization layer
110
is also shown in FIG.
1
. Although the second upper feature
110
b
is connected to a second upper conductive via
114
b
, the second upper conductive via
114
b
is not connected to a second lower feature
112
b
(i.e., it is floating) of the lower patterned metallization layer
112
. The second lower feature
112
b
is connected through a second lower conductive via
117
b
to the substrate.
In contrast to the aligned first upper feature
114
a
, the second upper feature
110
b
and second upper conductive via
114
b
are aligned along a second vertical axis
122
, while the second lower feature
112
b
and second lower conductive via
117
b
are aligned along a third vertical axis
124
. This serious misalignment may result in an open circuit between the second upper feature
110
b
and the substrate.
To measure this and other less serious misalignments, conventionally, a test wafer is taken out of a fabrication line after each pair of patterned metallization layers (e.g.,
110
and
112
) have been deposited and patterned. The test wafer is then probed at positions on the upper patterned metallization layer (e.g.,
110
b
) and the substrate to determine whether misalignments are present between the upper feature
110
b
and the substrate. Misalignment may be detected by measuring the voltage difference or resistance between the substrate and the upper feature
110
b
. Unfortunately, this probing may result in significant damage to the IC devices on the test wafer. As a result, the probing process may introduce significant levels of particle contamination to the test wafer. When such contamination occurs, the test wafer is most likely scrapped, and may not be reintroduced into the wafer processing line. This also has the side effect of increasing costs and thereby decreasing production yield.
Accordingly, in view of the foregoing, there is a need for a nondestructive methods of detecting layer-to-layer misalignments and an apparatus for implementing the nondestructive methods.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a technique for nondestructively testing and detecting misalignments in interconnect structures. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for inspecting electrical interconnections in a multi-level semiconductor device is disclosed. The method includes forming an interconnect structure in the multi-level semiconductor device. The interconnect structure has a lower metallization layer that lies in a lower level and an upper metallization layer that lies in an upper level. The method includes performing a passive voltage contrast operation using a scanning electron microscope to produce an image of the upper metallization layer of the interconnect structure. The method further includes inspecting the image produced by the scanning electron microscope to determine whether a misalignment is present in the interconnect structure.
In another embodiment, a semiconductor inspection apparatus for detecting misalignments in an interconnect structure is disclosed. The semiconductor inspection apparatus has a chamber having an electron column and a secondary electron detector. The apparatus further includes a stage for holding a substrate having the interconnect structure. The stage is configured to tilt the substrate, such that an electron beam that is emitted from the electron column is directed at the interconnect structure, and such that a plurality of secondary electrons are emitted off of the interconnect structure and detected by the secondary electron detector.
In yet another embodiment, a system for inspecting electrical interconnections in an interconnect structure of a multi-level semiconductor device is disclosed. The interconnect structure has a lower metallization layer that lies in a lower level and an upper metallization layer that lies in an upper level. The system includes a means for performing a pass
Harvey Ian R.
Sur, Jr. Harlan
Martine Penilla & Kim LLP
Metjahic Safet
Philips Electronics North America Corp.
Tang Minh
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