Microinstruction storage units employing partial address generat

Details Microinstruction storage units employing partial address generat Microinstruction storage units employing partial address generat

1978-06-30

1981-06-30

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

042765951

ABSTRACT:
A microcontroller having a novel addressing arrangement for addressing a storage means containing microinstructions is disclosed. The microcontroller has a fixed machine cycle time for executing each instruction and is arranged to fetch the next instruction during the execution of the current instruction. Branch, conditional branch and non-branch type of instructions are executed.
The means for executing instructions is characterized by a plurality of instruction addressable data sources which are selectively connected to the input of the ALU register during the input phase of the machine cycle and a plurality of instruction addressable data destinations which are selectively connected to the output of the ALU register during the output phase of the machine cycle.
The means for fetching the next instruction is characterized by a plurality of partial address generators, one of which is the ALU register employed to transfer data from a source to a destination. Control means responsive to the contents of an instruction register decoder supplies appropriate control signals at predetermined times to cause the transfer of address signals from the partial address generators to the address register to initiate readout of the next instruction from the instruction storage means during the execution of the current instruction.

REFERENCES:
patent: 3949370 (1976-04-01), Reyling, Jr. et al.
patent: 3956738 (1976-05-01), Tessera
patent: 4050058 (1977-09-01), Garlic
patent: 4053944 (1977-10-01), Dixon

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