Incrementer/decrementer circuit

Details Incrementer/decrementer circuit Incrementer/decrementer circuit

1979-08-09

1981-07-21

Anagnos, Larry N.

Boots, shoes, and leggings

307220C, 364747, G06F 750

Patent

active

042801907

ABSTRACT:
An increment/decrement circuit is provided which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/decrement circuit and also uses a reduced number of transistors. The increment/decrement circuit has a carry/borrow generator and has an increment/decrement output portion. The carry/borrow generator uses only three transistors plus an inverter and two coupling transistors. The increment/decrement output portion uses only six transistors.

REFERENCES:
patent: 3505511 (1970-04-01), Campano et al.
patent: 3989940 (1976-11-01), Kihara
patent: 4153939 (1979-05-01), Kudou
patent: 4218750 (1980-08-01), Carter et al.

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