Variable length decoder using serial and parallel processing

Details Variable length decoder using serial and parallel processing Variable length decoder using serial and parallel processing

1994-05-25

1996-02-13

Hoff, Marc S.

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

341 65, H08M 740

Patent

active

054914809

ABSTRACT:
The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.

REFERENCES:
patent: 4700175 (1987-10-01), Bledsoe
patent: 4853696 (1989-08-01), Mukherjee
patent: 5181031 (1993-01-01), Tong et al.
patent: 5225832 (1993-07-01), Wang et al.
patent: 5248356 (1995-06-01), Ozaki
patent: 5363097 (1994-11-01), Jan
A. Mukherjee, N. Ranganathan & M. Bassiouni, "Efficient VLSI Designs for Data Transformation or Tree-Based Codes" IEEE Trans. on Cirs. & Sys., vol. 88, No. 3, pp. 306-314 (1991).

Affiliated with

Also associated with

Rating

Variable length decoder using serial and parallel processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable length decoder using serial and parallel processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable length decoder using serial and parallel processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-243110