Boots – shoes – and leggings
Patent
1990-04-03
1994-09-20
Harrell, Robert B.
Boots, shoes, and leggings
395DIG1, 395425, 3642318, 3642328, 36424341, G06F 900
Patent
active
053496728
ABSTRACT:
A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.
REFERENCES:
patent: 3618041 (1971-11-01), Horikushi
patent: 3781823 (1973-12-01), Senese
patent: 3845474 (1974-10-01), Lange et al.
patent: 3859636 (1975-01-01), Cook
patent: 3979726 (1976-09-01), Lange et al.
patent: 4011547 (1977-03-01), Kimmel
patent: 4179736 (1979-12-01), Wilhite et al.
patent: 4274953 (1981-04-01), Douglas et al.
patent: 4295193 (1981-10-01), Pomerene
patent: 4312034 (1982-01-01), Gunter et al.
patent: 4322795 (1982-03-01), Lange et al.
patent: 4325121 (1982-04-01), Gunter et al.
patent: 4342078 (1982-07-01), Tredennick et al.
patent: 4367524 (1983-01-01), Budde et al.
patent: 4370710 (1983-01-01), Kroft
patent: 4399506 (1983-08-01), Evans et al.
patent: 4455602 (1984-06-01), Baxter, III et al.
patent: 4456954 (1984-06-01), Bullions, III et al.
patent: 4471429 (1984-09-01), Porter et la.
patent: 4471432 (1984-09-01), Wilhite et al.
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4502110 (1985-02-01), Saito
patent: 4521850 (1985-06-01), Wilhite et al.
patent: 4521851 (1985-06-01), Trubisky et al.
patent: 4530050 (1985-07-01), Fukunuga et al.
patent: 4551799 (1985-11-01), Ryan et al.
patent: 4602368 (1986-07-01), Circello et al.
patent: 4608633 (1986-08-01), Boothroyd et al.
patent: 4675806 (1987-06-01), Uchida
patent: 4695951 (1987-09-01), Hooker et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4710844 (1987-10-01), Thompson et al.
patent: 4713752 (1987-12-01), Tone
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4740889 (1988-04-01), Motersole et al.
patent: 4775955 (1988-10-01), Liu
MC68020 32 Bit Microprocessor User's Manual, 2nd Edition, Englewood Cliffs, NJ, Prentice-Hall, Inc., 1984, pp. 1-2, 1-9/1-10, 6-8, 6-9, 7-1 to 7-4.
Computing Survey, vol. 14, No. 3, Sep. 3, 1982, pp. 473-530, A. J. Smith, "Cache Memories".
Electronics International, vol. 55, No. 16, Aug. 1982, pp. 112-117, Per Knudsen, "Supermini Goes Microprocessor Route to Put It Up Front in Performance".
Computer Design, vol. 24, No. 3, Mar. 1985, pp. 173-181, T. Fossum et al., "New VAX Squeezes Mainframe Power into Mini Package".
"COMPCON 84", 28th IEEE Computer Society International Conference, digest of papers, Intellectual Leverage The Driving Technologies, Feb. 27, 1984, pp. 230-236, David Stevenson, Z80,000 32-Bit Microprocessor.
"Microcomputer Hardware", The Iwanami Microelectronics Course, Nov. 1984, Japan, pp. 144-145.
"A Cache Memory for the NS16032 Virtual Memory Memory Processor", R. S. Lim, 1984 IEEE, pp. 377-381.
"Integrated MMU, Cache/Raise System-Level Issues", Sorin Iacobovici et al., Computer Design, vol. 26, No. 10, May 15, 1987, pp. 75-79.
Hanawa Makoto
Hasegawa Atsushi
Kawasaki Ikuya
Nishimukai Tadahiko
Uchiyama Kunio
Harrell Robert B.
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
LandOfFree
Data processor having logical address memories and purge capabil does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processor having logical address memories and purge capabil, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processor having logical address memories and purge capabil will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2430595