Second order phase locked loop

Details Second order phase locked loop Second order phase locked loop

1993-03-31

1994-09-20

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 1A, 375120, H03L 7089

Patent

active

053493095

ABSTRACT:
A phase locked loop using an oscillating circuit for controlling the frequency by a digital signal according to the present invention comprises a loop filter. The loop filter includes a random walk filter 3, a counter 4, a register 5 and an adder 6. The oscillating circuit 7 emits a signal having a frequency corresponding to the output of the adder 6. Further, a phase/frequency detector 2 emits a phase lag signal LAG and a phase lead signal LEAD according to the phase difference between a signal IN provided to an input terminal 1 and a signal REF provided from the oscillating circuit 7 to thereby increase the degree of freedom for determining a loop constant while avoiding generation of the steady phase error relative to the frequency offset.

REFERENCES:
patent: 5057794 (1991-10-01), Shih
F. Gardner, "Charge-Pump Phase-Lock Loops", IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980, pp. 1849-1858.
C. Shih et al, "Jitter Attenuation Phase Locked Loop Using Switched Capacitor Controlled Crystal Oscillator", IEEE 1988 Custom Integrated Circuits Conference, pp. 9.5.1-9.5.3.
Electronics and Communications in Japan, vol. 70, No. 7, Jul. 1987, pp. 70-76, Hiroomi Hikawa et al, "Al Digital Phase-Locked Loop With a Wide Locking Range".
IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988, pp. 455-458, "Feed-Forward Compensation Circuit for Digital Random-Walk Filters".
Transactions of the Institute of Electronics, Information and Comm. Engineers of Japan, vol. E72, No. 2, Feb. 1989, pp. 111-117, Hiroomi Hikawa et al., "A Digital Phase-Locked Loop With a Low Frequency Clock".

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