Programmable t.sub.co circuit

Details Programmable t.sub.co circuit Programmable t.sub.co circuit

1993-03-08

1994-09-20

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 3072471, 3072722, 328 72, H03K 5135

Patent

active

053492552

ABSTRACT:
A circuit having a data path with a programmable clock-to-output delay time (t.sub.co). The circuit includes a master-slave flip-flop and selection/predriver logic circuitry whereby two select inputs can program the circuit into one of three different modes of operation. In a data-in mode, the input data is directly connected to the output driver, bypassing the flip-flop. In a fast mode, the circuit t.sub.co is reduced such that a higher frequency clock may be used. For low noise operation, the fast mode may be turned off to put the circuit in the regular mode, allowing the circuit to run at lower clock frequencies.

REFERENCES:
patent: 3812384 (1974-05-01), Skorup
patent: 4797575 (1989-01-01), Lofgren
patent: 5136180 (1992-08-01), Caviasca et al.
patent: 5159278 (1992-10-01), Mattison

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