Method of fabricating a bottom and top gated thin film transisto

Details Method of fabricating a bottom and top gated thin film transisto Method of fabricating a bottom and top gated thin film transisto

1993-06-10

1994-09-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 56, 437915, 148DIG131, 148DIG150, H01L 21265

Patent

active

053488997

ABSTRACT:
An electric interconnection method includes: a) providing two conductive layers separated by including material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

REFERENCES:
patent: 5015599 (1991-05-01), Verhaar
patent: 5064776 (1991-11-01), Roberts
patent: 5100816 (1992-03-01), Rodder
patent: 5112765 (1992-05-01), Cederbaum et al.
patent: 5155054 (1992-10-01), Itoh
Colinge, J. P., et al., "Silicon-On-Insulator `Gate-All-Around Device`", IEEE, IEDM 90-595-599 (1990).
Tanaka, T. et al., "Analysis of P.sup.+ PolySi Double-Gate Thin-Film SOI MOSFETs", IEEE, IEDM 91-683-686, (1991).

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