Transistor fabrication methods using overlapping masks

Details Transistor fabrication methods using overlapping masks Transistor fabrication methods using overlapping masks

1992-12-01

1994-09-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 21, 437147, 437918, H01L 21266

Patent

active

053488970

ABSTRACT:
Transistor fabrication methods are provided which are suitable, for example, for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment in which the channel region overlies the gate, a first mask is formed over the channel region, and then an LDD implant is carried out. A second mask is then formed over the LDD portion of the drain region. The second mask is allowed to extend over the first mask. A heavy doping implant is then carried out. Thus an LDD structure can be provided on the drain side but not on the source side with only one mask--the first mask--defining the channel length. In some embodiments, both masks include photoresist. The first photoresist mask is hardened to prevent its lifting during development of the resist of the second mask. Further, after the LDD implant, the first photoresist mask is outgassed to improve the adhesion of the second photoresist mask. In another embodiment, the second mask is used to pattern the first mask. The patterning etch undercuts the second mask. After the heavy doping implant, the second mask is removed, and the LDD implant is performed with the first mask masking the channel region.

REFERENCES:
patent: 4244752 (1981-01-01), Henderson, Sr. et al.
patent: 5064775 (1991-11-01), Chang
patent: 5114869 (1992-05-01), Tanaka et al.
patent: 5124774 (1992-06-01), Godinho et al.
patent: 5151374 (1992-09-01), Wu
patent: 5166771 (1992-11-01), Godinho et al.
Article by T. Yamanaka et al. entitled "A 25 .mu.m.sup.2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity", IEDM 88, pp. 48-51, 1988.

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