Nonvolatile memory device capable of reading data with a reduced

Details Nonvolatile memory device capable of reading data with a reduced Nonvolatile memory device capable of reading data with a reduced

1997-03-27

1999-08-31

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518509, 36518511, 36518525, 365210, 365233, 365194, G11C 1606

Patent

active

059462370

ABSTRACT:
A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing component that are adapted to receive the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices. Each one of the two half-matrices has a reference line that is adapted to constitute a reference for reading the other half-matrix. The data sensing component receives the data from one half-matrix and the reference from the other half-matrix and is adapted to transmit, according to a control timing, the data on an internal bus.

REFERENCES:
patent: 5022009 (1991-06-01), Terada et al.
European Search Report from European Patent Application 96830162.2, filed Mar. 29, 1996.
IEEE International Solid State Circuits Conference, vol. 36, Feb. 1993, New York US, pp. 42-43, Rosendale et al., "A 13ns Mb CMOS EPROM Using 1-T FAMOS Technology".

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