Nonvolatile semiconductor memory device having the reliability o

Details Nonvolatile semiconductor memory device having the reliability o Nonvolatile semiconductor memory device having the reliability o

1998-09-17

1999-08-31

Nelms, David

Static information storage and retrieval

Floating gate

365182, 365149, 257314, 257315, 257321, G11C 1604

Patent

active

059462302

ABSTRACT:
An EEPROM includes a memory cell array section and a peripheral driving circuit section. The memory cell array section has memory cells which are arranged in a matrix form on a silicon substrate and each of which includes a floating gate coupled to the silicon substrate via a first capacitor having a first gate insulating film as a dielectric and a control gate coupled to the floating gate via a second capacitor having a second gate insulating film as a dielectric. In the outmost portion of the memory cell array section, memory cells of a first group are arranged and memory cells of a second group are arranged in the central portion on the inner side of the memory cell array section. The first gate insulating film of the first group of memory cells is thicker than the first gate insulating film of the second group of memory cells. The peripheral driving circuit section is formed adjacent to the memory cell array section on the silicon substrate. The circuit section is to activate the storage function of the memory cell array section and includes a row decoder, sense amplifier circuit, source line potential control circuit and the like.

REFERENCES:
patent: 4612629 (1986-09-01), Harari
Aritome, et al. "A 0.67um.sup.2 Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) For 3V-only 256 Mbit NAND EEPROMs," IEEE (IEDM) 1994, ISBN 0-7803-2111-1, pp. 94-61 to 94-64.

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