System for dynamically providing predicted high/slow speed acces

Details System for dynamically providing predicted high/slow speed acces System for dynamically providing predicted high/slow speed acces

1989-06-02

1992-05-12

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642329, 36424232, 364244, 3642558, 3649481, 3649556, 3649585, 273 85G, 3652301, G06F 1202, G06F 1200

Patent

active

051135116

ABSTRACT:
A system (60) for predicting CPU addresses includes a CPU (34) connected by bus (62) to page mode address predicting circuit (64). The page mode address predicting circuit (64) is connected to memory arbitration circuits (66) by bus (68). The memory arbitration circuits (66) are connected to RAM (42) by address, data and control busses (44), (46) and (48). The CPU (34), page mode address predicting circuit (64) and the memory arbitration circuits 66 are contained in a microprocessor integrated circuit (32). The page mode predicting circuit 64 examines signals from the CPU (34) to be supplied to the data bus (46) at the time of a SYNC pulse. This operation results in examination of the first byte of a CPU instruction to determine how many of the following memory accesses will be able to be carried out in high speed mode. If it is determined that the next memory access will be able to be carried out in the high speed mode, then the next memory cycle is performed using a high speed access mode of the RAM (42), e.g. page mode access.

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