Semiconductor device having a conductor through an inter-level l

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257280, 257281, 257700, 257759, 257752, 257753, 257754, 257755, 257756, 257757, 257748, 257781, 257643, 257750, H01L 2348

Patent

active

059457392

ABSTRACT:
A multi-layered wiring structure includes a lower wiring having an upper surface, a first inter-level insulating layer having a first flat upper surface substantially coplanar with the upper surface of the lower conductive wiring and a recess contiguous to the first flat upper surface, a spin-on-glass layer filling the recess and having a second flat upper surface substantially coplanar with the first flat upper surface, a second inter-level insulating layer covering the first and second flat surfaces and the upper surface of the lower conductive wiring and an upper conductive wiring extending on the second inter-level insulating layer and passing through a contact hole of the second inter-level insulating layer so as to be held in contact with the lower conductive wiring, and the first and second flat upper surfaces are created through an etch-back using gaseous etchant equally etching the first inter-level insulating layer and the spin-on-glass layer, thereby creating smooth surface under the second inter-level insulating layer.

REFERENCES:
patent: 5094965 (1992-03-01), Ozaki et al.
patent: 5306947 (1994-04-01), Adachi et al.
patent: 5705856 (1998-01-01), Wakabayashi
Japanese Office Action dated May 19, 1998 with English language translation of Japanese Examiner's comments.

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