Method for fabrication of shallow isolation trenches with sloped

Details Method for fabrication of shallow isolation trenches with sloped Method for fabrication of shallow isolation trenches with sloped

1997-12-19

1999-08-31

Dang, Trung

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438424, 438433, 148DIG50, H01L 21302

Patent

active

059453524

ABSTRACT:
The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.

REFERENCES:
patent: 4857477 (1989-08-01), Kanamori
patent: 5674775 (1997-10-01), Ho et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 5807789 (1998-09-01), Chen et al.

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