FPGA input output buffer with registered tristate enable

Details FPGA input output buffer with registered tristate enable FPGA input output buffer with registered tristate enable

1997-04-08

1999-08-31

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

710 56, 326 37, 326 56, G06F 1300

Patent

active

059448130

ABSTRACT:
In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

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