Method of forming a narrow polysilicon gate with i-line lithogra

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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Details

438694, 438736, 438942, 438947, H01L21/302

Patent

active

059021330

ABSTRACT:
A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a second oxide mask having a second feature size one half the width of the first feature size. All of the capping oxide layer is removed except for the first and second oxide masks. The second photomask is removed. The feature layer is etched through where it is not covered by the first and second oxide masks to form the first and second features having the second line width of one half the resolution of the photolithography process in the manufacture of an integrated circuit device.

REFERENCES:
patent: 4414057 (1983-11-01), Bourassa et al.
patent: 5013398 (1991-05-01), Long et al.
patent: 5597764 (1997-01-01), Koh et al.

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