Method and apparatus for preventing incorrect fetching of an ins

Details Method and apparatus for preventing incorrect fetching of an ins Method and apparatus for preventing incorrect fetching of an ins

Filed on

1994-12-05

Date issued

1995-07-18

Examiner

Lall, Parshotam S.

Other Related Categories

G06F 930

Type

Patent

Status

active

Patent number

054349877

Description

ABSTRACT:
A number of identical matching circuits are integrated into the store address buffer, one matching circuit to each buffer slot, for generating a number of match signals, one for each detected match, using at most the entire source address of an instruction being fetched and the corresponding portions of the store destination addresses of the buffered store instructions. Additionally, a stall signal generator complimentary to the store address buffer is provided for generating a single stall signal for the bus controller, using the match signals, thereby stalling an instruction fetch from a source address that is potentially a store destination of one of the buffered store instructions with minimal performance cost.

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"The Metaflow Architecture", .COPYRGT. 1991 IEEE, Jun. IEEE Micro, Authors: Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, David Isaman.

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