Scan linearity correction

Details Scan linearity correction Scan linearity correction

1984-08-03

1989-08-22

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 102

Patent

active

048602370

ABSTRACT:
A method for generating a variable frequency clock pulse for a raster scanner. First, a correction number, which may be the sum of corrections for scan-nonlinearity, polygon signature errors and motor hunt errors, is generated. This number is then added periodically to a running sum. The most significant bit of this sum is then available as the clock pulse output. The frequency of the output clock will be proportional to the correction number. The described circuit uses an accumulating adder and a register loop to form an accumulator circuit. The correction number is then supplied to the other accumulator adder input, and the register is clocked with a fixed frequency sample clock pulse.

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Richards, Arithmetic Operations in Digital Computers, pp. 303-311, D. Van Nostrand Co. Inc., Princeton, NJ 1961.

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