Semiconductor memory device comprising trench memory cells

Details Semiconductor memory device comprising trench memory cells Semiconductor memory device comprising trench memory cells

1987-12-11

1989-08-22

Hille, Rolf

357 55, 357 49, 357 41, H01L 2978, H01L 2906, H01L 2712, H01L 2702

Patent

active

048600709

ABSTRACT:
A plurality of memory cells are arranged spaced apart from each other on the surface of a semiconductor substrate. Cell trenches are formed corresponding to the memory cells on the semiconductor substrate. An isolation trench formed to be integral with the cell trenches is formed in a region between each of the cell trenches in each of memory cells and the cell trench in the adjacent memory cell. Charge storage regions are formed in the bottom surface portions and the side surface portions of the cell trenches, and isolation oxide films are formed in the bottom surface portion and the side surface portion of the isolation trench.

REFERENCES:
patent: 4017885 (1977-04-01), Kendall et al.
patent: 4577395 (1986-03-01), Shibata
Mashiko et al., "A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 643-650.
Elahy, M. et al., "Trench Capacitor Leakage in MBIT DRAMS", IEDM 84, 9.6, pp. 248-251.

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