Preferential oxidization self-aligned contact technology

Details Preferential oxidization self-aligned contact technology Preferential oxidization self-aligned contact technology

1991-01-14

1992-05-19

Wojciechowicz, Edward J.

Fishing, trapping, and vermin destroying

357 234, 357 239, 357 52, 357 55, 437 15, 437 34, 437 27, 437 41, 437 57, 437192, 437235, H01L 2702, H01L 21265

Patent

active

051152967

ABSTRACT:
A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit has a substrate doped with a first conductivity. The substrate has field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device. Opposite type conductivity ions are implanted into the doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor. Dielectric spacers are formed on the sidewalls of the dielectric/gate electrode structures. A block out mask is formed over the source/drain regions designated to have self-aligned contacts made thereto. Opposite type conductivity ions are implanted into the substrate to form heavily doped portions to complete the formation of the source/drain regions in those nondesignated self-aligned contact regions. The block out mask is removed. The structure is subjected to an oxidizing atmosphere to preferentially oxidize polysilicon gate regions and heavily doped source/drain regions (thicker silicon dioxide) is compared to the lightly doped source/drain regions (thinner silicon dioxide). Opposite type conductivity ions are implanted into the doped subtrate to form heavily doped portion and to complete the formation of the source/drain regions in those designated self-aligned contact regions. Chemical dip etching is used to remove thin oxide over the designated self-aligned contact source/drain regions while leaving the thicker oxide layer remaining over the nondesignated source/drain regions. The appropriate metallurgy is provided to the designated self-aligned regions to electrically connect MOS field effect transistors into a desired integrated circuit.

REFERENCES:
patent: 4804636 (1989-02-01), Groover et al.
patent: 4822749 (1989-04-01), Flanner et al.
patent: 4949136 (1990-08-01), Jain

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