Power-on reset circuit for controlling test mode entry

Details Power-on reset circuit for controlling test mode entry Power-on reset circuit for controlling test mode entry

1990-08-17

1992-05-19

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307594, H03K 1722

Patent

active

051151464

ABSTRACT:
A power-on reset circuit is disclosed, of the type having a latch which powers up into a preferred state, and which also has a timed switch for switching the latch after a selected duration of time following the power supply voltage reaching a threshold level. The disclosed power-on reset circuit further includes a reset circuit for discharging the output node of the latch upon loss of an adequate level for the power supply voltage. The reset circuit includes a discharging transistors which has its gate biased to a voltage above that of the threshold voltage of the discharging transistor, so that full discharge of the output of the latch is ensured. Alternate configurations of the reset circuit are disclosed. In each case, the timed switch is also re-enabled by the operation of the reset circuit so that the power-on reset circuit is ready to respond to renewed powering-up of the power supply voltage. The disclosed power-on reset circuits, including the reset circuit, thus provide full and prompt reset of the power-on signal even in the event of brief power supply loss.

REFERENCES:
patent: 4446381 (1984-05-01), Dalrymple
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4788454 (1988-11-01), Tanagawa et al.
patent: 4797584 (1989-01-01), Agati et al.
patent: 4860259 (1989-08-01), Tobita
patent: 4866984 (1989-12-01), Nakaoka
McAdams, et al., "A 1-Mbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Journal of Solid-State Circuits (Oct. 1986), vol. SC-21, No. 5, pp. 635-642.
Shimada, et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits (Feb. 1988), vol. 23, No. 1, pp. 53-58.

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