System and method for error detection and reducing simultaneous

Details System and method for error detection and reducing simultaneous System and method for error detection and reducing simultaneous

1994-03-07

1996-01-02

Beausoliel, Jr., Robert W.

Excavating

371 64, 341 58, 326 26, G06F 1100, H03M 1300

Patent

active

054815550

ABSTRACT:
A system and method that reduces the simultaneous switching noise of outputs and the processing delays caused by inductance by using an encoding scheme that results in a net signaling current of substantially zero at each cycle time for the fast parallel switching networks of digital integrated circuit chips and that provides multiple types of error detection.

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