Method of forming vertical gate thin film transistors in liquid

Details Method of forming vertical gate thin film transistors in liquid Method of forming vertical gate thin film transistors in liquid

1988-02-04

1989-08-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 59, 357 40, 357 234, 357 41, 357 237, H01L 2702, H01L 2978

Patent

active

048596230

ABSTRACT:
Vertical gate thin film transistors are integrated into an actively addressable liquid crystal array to provide the switching function for charging each pixel element and any desired peripheral transistor circuitry. One of the conductive plates of each pixel of the array includes an extended portion. The address lines for the switching/charging transistors form a grid between the rows and columns of pixels and each intersection of the grid lies on an extended portion of a pixel element with the drain of the associated transistor formed directly on the extended portion. The source of the transistor is that portion of one set of address lines lying superjacent but insulated from the transistor drain. The gate of the transistor is that portion of the second set of address lines which is adjacent but insulated from the edges of the source and drain, lying essentially perpendicular to the substrate. Additional transistors for the peripheral circuitry are formed by the same process steps which form the pixel elements and the switching transistor.

REFERENCES:
patent: 3863332 (1975-02-01), Leupp et al.
patent: 4009061 (1977-02-01), Simon
patent: 4320190 (1982-03-01), Ruedin
patent: 4332075 (1982-06-01), Ota et al.
patent: 4470060 (1984-09-01), Yamazaki
patent: 4547789 (1985-10-01), Cannella et al.
VLSI Technology by S. M. Sze, 1983, pp. 356 and 358.
VLSI Technology by S. M. Sze, 1983, p. 305, Fig. 1.

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