Manufacturing method of well region in coms intergrated circuit

Details Manufacturing method of well region in coms intergrated circuit Manufacturing method of well region in coms intergrated circuit

1990-08-01

1992-05-19

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 56, 437 70, 148DIG9, 357 42, H01L 21265

Patent

active

051148684

ABSTRACT:
First, N-type channel stoppers are formed in an element formation region of a P-channel MOS transistor and in an element isolation region of the P-channel MOS transistor, of a CMOS transistor. After forming a field oxide film, an N well is formed in the element formation region of the P-channel MOS transistor. In spite of the fact that the dose of ions used for the formation of an N-type channel stopper is smaller than the dose of ions used for the formation of an N well, the surface concentration of the N-type impurity of the N-type channel stopper is higher than that of the N well. The N-type impurity concentration in the portion where the N-type channel stopper and the N well are brought into contact, becomes uniform. The variability in the threshold voltage of the P-channel MOS transistor, the threshold voltage of the P-channel parasitic MOS transistor, the junction breakdown voltage of the P.sup.+ diffused layer and the junction capacitance of the P.sup.+ diffused layer is reduced, so that the device obtained is suited for the submicron process.

REFERENCES:
patent: 4549340 (1985-10-01), Nagasawa et al.
patent: 4839301 (1989-06-01), Lee
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4927776 (1990-05-01), Soejima
patent: 4929565 (1990-05-01), Parrillo
patent: 5024961 (1991-06-01), Lee et al.

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