Method and structure for providing error correction code for 8-b

Details Method and structure for providing error correction code for 8-b Method and structure for providing error correction code for 8-b

1993-12-30

1996-01-02

Envall, Jr., Roy N.

Excavating

371 371, H03M 1300

Patent

active

054815525

ABSTRACT:
The present invention relates to a method and structure for implementing a 64/8 ECC algorithm on a SIMM using a computer which has a 32-bit bus and is configured with a 36-bit wide memory. This is accomplished by writing two successive 4 byte words from the system to latches, to form an 8 byte quad word, and writing 8 check bits utilizing the entire 64 bits of the quad word. One-half of the quad word (i.e., 32 bits) together with 4 of the 8 check bits for a total of 36 bits is stored at one address location in memory, and the remaining 32 bits of the quad word, together with the remaining 4 check bits, are stored at another, preferably the successive 36 bit, address location in memory. When the quad word and check bits are read from the memory, they are read serially, i.e., the first 32 bits and 4 associated check bits are read and latched, followed by the second 32 bits and the 4 associated check bits being read and combined with the first 32 bits of data and 4 check bits so as to essentially "reconstitute" the original 64-bit quad word with 8 check bits. From the "reconstituted" 64-bit data word and 8 check bits, the error correction is performed. The 64-bit quad word with the corrected data is latched and asserted successively on the data bus as two 32-bit words. Also, preferably logic and circuitry to perform a read-modify-write (R-M-W) function are provided.

REFERENCES:
patent: 5235693 (1993-08-01), Chinnaswamy et al.
patent: 5283877 (1994-02-01), Gastinel et al.
patent: 5313475 (1994-05-01), Cromer et al.
patent: 5331645 (1994-07-01), Miller et al.
patent: 5335234 (1994-08-01), Matteson et al.
patent: 5430742 (1995-07-01), Jeddeloh et al.

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