Synchronous type semiconductor memory

Details Synchronous type semiconductor memory Synchronous type semiconductor memory

1993-04-12

1994-05-10

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365236, 365194, G11C 11402, G11C 2900

Patent

active

053114833

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a synchronous type semiconductor memory, particularly to an output control system of a synchronous type dynamic random access memory (hereinafter referred to as DRAM).


BACKGROUND TECHNOLOGY

A conventional synchronous type semiconductor memory is disclosed in Japanese Laid-Open Patent Publication No. 61-39295 and No. 62-275384.
The synchronous type semiconductor memory has a memory cell array in which memory cells are arranged in rows and columns.
A decoder is coupled to an input of the memory cell array. A latch circuit and an output buffer are coupled to an output of the memory cell array. When data is read from the memory cell array, externally generated input addresses are decoded by a decoder so that one of the memory cells is selected in the memory cell array. Data stored in the thus selected memory cell is latched temporarily in the latch circuit. The data latched being synchronized with a synchronous clock is thereafter read out via the output buffer. In a synchronous type static random access memory (hereinafter referred to as SRAM), one pulse alone of a synchronous clock is supplied to the output buffer during a memory access time so that the read data can be accurately output in synchronism with the clock pulse. access starting time to the time when the latch completion signal is generated, and a delay clock number output circuit for outputting the output of the clock counter circuit to an external device.
A second aspect of the present invention comprises a DRAM which selects a memory cell by decoding an address and performs writing data in or reading data from the memory cell, wherein the DRAM further comprises a data latch circuit for latching the data read from the memory cell, an output clock delay control circuit for generating an output control signal.,in response to the number of delay clocks which are set by a synchronous clock and an external input signal, and an output circuit for outputting the read data, which is latched by the data latch circuit, in response to the output control signal.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an arrangement of a synchronous type DRAM according to a first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a clock counter circuit and a delay clock number output circuit,
FIG. 3 is a timing chart of FIG. 1,
FIG. 4 is a block diagram showing an arrangement of a synchronous type DRAM according to a second embodiment of the present invention,
FIG. 5 is a timing chart of FIG. 4,
FIG. 6 is a block diagram showing an arrangement of a synchronous type DRAM according to a third embodiment of the present invention,
FIG. 7 is a circuit diagram of an output clock delay control circuit in FIG. 6, and
FIG. 8 is a timing chart of FIG. 6.


BEST MODE FOR CARRYING OUT THE INVENTION

A plurality of pulses of consecutive synchronous clocks are input to the output buffer during a memory access time in the DRAM. If the conventional synchronization system is applied to the DRAM, it is necessary to previously determine which pulse of the synchronous clock should be selected to output the read data via the output buffer in response thereto.
In the DRAM, since an input of the address and the reading or writing of the data are performed during a memory access time, there is a possibility of generating the lag of the time when the read data is applied to the latch circuit. Accordingly, it is impossible to accurately control the action timing of the output buffer in the DRAM which employs the conventional synchronization system.
It is an object of the present invention to provide a synchronous type DRAM which selects an optimal pulse among a plurality of pulses of the synchronous clocks during a memory access time to determine the operating timing of the output buffer.
It is another object of the present invention to provide a synchronous type DRAM which can perform the accurate synchronous control.


DISCLOSURE OF THE INVENTION

A first aspect of the present invention compr

REFERENCES:
patent: 4970693 (1990-11-01), Nozaki et al.
patent: 4985868 (1991-01-01), Nakano et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 5, Oct. 1987, New York U.S., pp. 161-162, `Self-timed performance test for stand-alone random-access memories` & Patent Abstracts of Japan, vol. 5, No. 104 (P-069), Jul. 1981.
IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, New York U.S., pp. 47-49, `Method providing wait-state processor cycles using medium speed dynamic RAM` p. 49, lines 5-19; FIGS. 1,2.

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