Method and apparatus for EEPROM negative voltage wordline decodi

Details Method and apparatus for EEPROM negative voltage wordline decodi Method and apparatus for EEPROM negative voltage wordline decodi

1992-12-16

1994-05-10

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365185, 365218, 365900, G11C 800

Patent

active

053114809

ABSTRACT:
A method and apparatus for negative wordline decoding in a flash EEPROM (10) is provided. In particular, a predecoder (26) generates a predecoding signal based on address and invert inputs. The predecoding signal is used to select wordlines in both positive and negative voltage decoding modes. Each wordline has associated with it a driver (28). The driver (28) receives the predecoding signal and is operable to drive the associated wordline high in response to the appropriate predecoding signal. Wordlines also have associated with them negative charge pumps (32). Each charge pump (32) is operable to drive the associated wordline negative when the driver (28) is not driving the wordline positive.

REFERENCES:
patent: 4823318 (1989-04-01), D'Arrigo et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5214606 (1993-05-01), Hashimoto
Miyawaki et al., "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories," IEEE Journal of Solid State Circuit, vol. 27, No. 4, Apr. 1992, pp. 583-588.
Mike McConnell, et al., "An Experimental 4-Mb Flash EEPROM with Sector Erase," IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, pp. 484-491.
Harvey Stiegler, et al. "A 4Mb 5V-Only Flash EEPROM with Sector Erase," IEEE Symposium on VLSI Circuits, 1990, pp. 103-104.

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