Vector multiplier having parallel carry save adder trees

Details Vector multiplier having parallel carry save adder trees Vector multiplier having parallel carry save adder trees

1986-10-20

1989-01-17

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

047991836

ABSTRACT:
High and low order bit carry propagation adders are connected to outputs of carry save adder trees which produce half-sums and half-carries. Following carry propagation addition of the low order bits carry propagation addition of the high order bits is carried out. A carry from the low order bit carry propagation addition is added to the high order bit carry propagation addtion.

REFERENCES:
patent: 4041292 (1977-08-01), Kindell
patent: 4228520 (1980-10-01), Letteney et al.
patent: 4525796 (1985-06-01), Omoda et al.
patent: 4644491 (1987-02-01), Ookawa et al.
Waser et al., "Real-Time Processing Gains Ground with Fast Digital Multiplier" Electronics, Sep. 29, 1977, pp. 93-99.
Anderson et al., "The IBM System/360 Model 91: Floating-Point Execution Unit", IBM Journal, pp. 34-53, Jan. 1967.

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